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From: Chen Gong <gong.chen@linux.intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: tony.luck@intel.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] x86/MCE: Update MCE severity condition check
Date: Fri, 21 Jun 2013 08:38:58 -0400	[thread overview]
Message-ID: <20130621123857.GA2784@gchen.bj.intel.com> (raw)
In-Reply-To: <20130620094152.GJ32694@pd.tnic>

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On Thu, Jun 20, 2013 at 11:41:52AM +0200, Borislav Petkov wrote:
> Date: Thu, 20 Jun 2013 11:41:52 +0200
> From: Borislav Petkov <bp@alien8.de>
> To: Chen Gong <gong.chen@linux.intel.com>
> Cc: tony.luck@intel.com, linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] x86/MCE: Update MCE severity condition check
> User-Agent: Mutt/1.5.21 (2010-09-15)
> 
> On Thu, Jun 20, 2013 at 05:16:12AM -0400, Chen Gong wrote:
> > Update some SRAR severity conditions check to make it clearer,
> > according to latest Intel SDM Vol 3(June 2013), table 15-20.
> > 
> > Signed-off-by: Chen Gong <gong.chen@linux.intel.com>
> > ---
> >  arch/x86/kernel/cpu/mcheck/mce-severity.c |   15 +++++----------
> >  1 file changed, 5 insertions(+), 10 deletions(-)
> > 
> > diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
> > index beb1f16..1fa12ea 100644
> > --- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
> > +++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
> > @@ -110,22 +110,17 @@ static struct severity {
> >  	/* known AR MCACODs: */
> >  #ifdef	CONFIG_MEMORY_FAILURE
> >  	MCESEV(
> > -		KEEP, "HT thread notices Action required: data load error",
> > -		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
> > -		MCGMASK(MCG_STATUS_EIPV, 0)
> > +		KEEP, "Action required but non-affected thread is continuable",
> > +		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR),
> > +		MCGMASK(MCG_STATUS_RIPV, MCG_STATUS_RIPV)
> >  		),
> >  	MCESEV(
> > -		AR, "Action required: data load error",
> > +		AR, "Action required: data load error on user land",
> 
> You mean "data load error in a user process"?

Yes it is.
> 
> >  		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_DATA),
> >  		USER
> >  		),
> >  	MCESEV(
> > -		KEEP, "HT thread notices Action required: instruction fetch error",
> > -		SER, MASK(MCI_STATUS_OVER|MCI_UC_SAR|MCI_ADDR|MCACOD, MCI_UC_SAR|MCI_ADDR|MCACOD_INSTR),
> > -		MCGMASK(MCG_STATUS_EIPV, 0)
> > -		),
> > -	MCESEV(
> > -		AR, "Action required: instruction fetch error",
> > +		AR, "Action required: instruction fetch error on user land",
> 
> ditto?
> 
ditto

> -- 
> Regards/Gruss,
>     Boris.
> 
> Sent from a fat crate under my desk. Formatting is fine.
> --

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  reply	other threads:[~2013-06-21 12:47 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-06-20  9:16 Chen Gong
2013-06-20  9:41 ` Borislav Petkov
2013-06-21 12:38   ` Chen Gong [this message]
2013-06-25  6:32 ` Naveen N. Rao
2013-06-25 16:31   ` Luck, Tony
2013-06-25 20:08     ` Naveen N. Rao
2013-06-26  9:18     ` Chen Gong
     [not found]       ` <0134840@agluck-desk.sc.intel.com>
2013-06-26 19:08         ` [PATCH] x86/mce: " Borislav Petkov
2013-06-26 20:23           ` Luck, Tony
2013-06-26 20:36             ` Borislav Petkov
2013-06-26 21:00               ` Luck, Tony
2013-06-26 21:10                 ` Borislav Petkov
2013-06-27  6:42                   ` Chen Gong
2013-06-27  8:55         ` Naveen N. Rao

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