Re: MTRR use in drivers

[Henrique de Moraes Holschuh <hmh@hmh.eng.br>]

On Sun, 23 Jun 2013, H. Peter Anvin wrote:
> On 06/23/2013 02:56 PM, Henrique de Moraes Holschuh wrote:
> > 
> > And as far as I could find from Intel's not-that-complete public
> > "specification updates", we are applying the errata workaround to a few more
> > processors than strictly required, but since I have no idea how to write a
> > test case, I can't whitelist the 3rd-gen Pentium M on my T43, nor can I get
> > ThinkPad owners to test it for us on 1st and 2nd-gen Pentium M and report
> > back.
> 
> Which specific erratum are you referring to, here?  The "WC becomes UC"
> erratum?  I don't think there is a sane testcase for it since it needs a
> very complicated setup to trigger.

There are at least two different nasty PAT issues that are not always
critical, and one that outright hangs the processor (if the unsupported
aliasing of WB with UC/WC happens).

Interestingly enough, most of the P4-Xeons and P4 do not appear to have the
"WC becomes UC" errata.

However, LOTS of P4, M-P4, Xeon PIII, Xeon, and Pentium M have a bug where
the four highest entries in the PAT table are inactive (aliased to the four
lowest entries) in mode B (PSE) and mode C (PAE) for 4k pages.  They work
fine for large pages.

Also, lots of them can hang if you ever alias WB with UC or WC (which is
apparently an unsupported configuration anyway, or so it says in the
errata).

There are other weird aliasing nasties, such as one where you get memory
corruption if you alias WB data with code (being accessed as UC or WC) in
the same cacheline, and some stuff such as weirdness should the page table
be on WC memory...

I can track down most of the CPUIDs involved if you want, but someone from
Intel would be better (I assume they actually have access to the errata
documentation in some less idiotic way than reading a ton of badly indexed
PDFs that take forever to find in their site).

-- 
  "One disk to rule them all, One disk to find them. One disk to bring
  them all and in the darkness grind them. In the Land of Redmond
  where the shadows lie." -- The Silicon Valley Tarot
  Henrique Holschuh