From: Peter Zijlstra <peterz@infradead.org>
To: "Yan, Zheng" <zheng.z.yan@intel.com>
Cc: linux-kernel@vger.kernel.org, mingo@elte.hu, eranian@google.com,
ak@linux.intel.com
Subject: Re: [PATCH 2/2] perf, x86: Add Silvermont (22nm Atom) support
Date: Thu, 18 Jul 2013 11:26:27 +0200 [thread overview]
Message-ID: <20130718092627.GG27075@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <1374138144-17278-2-git-send-email-zheng.z.yan@intel.com>
On Thu, Jul 18, 2013 at 05:02:24PM +0800, Yan, Zheng wrote:
> +static struct event_constraint intel_slm_event_constraints[] __read_mostly =
> +{
> + FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
> + FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
> + FIXED_EVENT_CONSTRAINT(0x013c, 2), /* CPU_CLK_UNHALTED.REF */
> + FIXED_EVENT_CONSTRAINT(0x0300, 2), /* pseudo CPU_CLK_UNHALTED.REF */
> + EVENT_CONSTRAINT_END
> +};
I'm still missing the fixup for intel_pmu_init() that will make this
actually work -- and the comment to clarify that yes slm really does
count them the same.
next prev parent reply other threads:[~2013-07-18 9:26 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-18 9:02 [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X Yan, Zheng
2013-07-18 9:02 ` [PATCH 2/2] perf, x86: Add Silvermont (22nm Atom) support Yan, Zheng
2013-07-18 9:26 ` Peter Zijlstra [this message]
2013-07-18 12:18 ` Stephane Eranian
2013-09-02 7:41 ` [tip:perf/core] perf/x86: " tip-bot for Yan, Zheng
2013-08-19 1:26 ` [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X Yan, Zheng
2013-08-19 14:24 ` Stephane Eranian
2013-08-19 14:39 ` Peter Zijlstra
2013-09-02 7:41 ` [tip:perf/core] perf/x86: " tip-bot for Yan, Zheng
2013-07-19 2:46 [PATCH 2/2] perf, x86: Add Silvermont (22nm Atom) support Yan, Zheng
2013-08-19 1:26 ` Yan, Zheng
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