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From: Peter Zijlstra <peterz@infradead.org>
To: Stephane Eranian <eranian@google.com>
Cc: "Yan, Zheng" <zheng.z.yan@intel.com>,
	LKML <linux-kernel@vger.kernel.org>,
	"mingo@elte.hu" <mingo@elte.hu>,
	"ak@linux.intel.com" <ak@linux.intel.com>
Subject: Re: [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X
Date: Mon, 19 Aug 2013 16:39:24 +0200	[thread overview]
Message-ID: <20130819143924.GG24092@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <CABPqkBRjJDOcFWOvZw6CTokrLbg5X=p8KCxZYQ47yRGYbdY_Pg@mail.gmail.com>

On Mon, Aug 19, 2013 at 04:24:56PM +0200, Stephane Eranian wrote:
> On Thu, Jul 18, 2013 at 11:02 AM, Yan, Zheng <zheng.z.yan@intel.com> wrote:
> > From: "Yan, Zheng" <zheng.z.yan@intel.com>
> >
> > Silvermont (22nm Atom) has two offcore response configuration MSRs,
> > unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
> > To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
> > define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event code
> > for OFFCORE_RSP_N by x86_pmu.extra_regs[N].event.
> >
> > Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com>
> 
> Works for me on IVB and NHM.
> 
> Reviewed-by: Stephane Eranian <eranian@google.com>

Thanks guys, and sorry for getting them lost in the inbox :/

  reply	other threads:[~2013-08-19 14:39 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-18  9:02 Yan, Zheng
2013-07-18  9:02 ` [PATCH 2/2] perf, x86: Add Silvermont (22nm Atom) support Yan, Zheng
2013-07-18  9:26   ` Peter Zijlstra
2013-07-18 12:18   ` Stephane Eranian
2013-09-02  7:41   ` [tip:perf/core] perf/x86: " tip-bot for Yan, Zheng
2013-08-19  1:26 ` [PATCH 1/2] perf, x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X Yan, Zheng
2013-08-19 14:24 ` Stephane Eranian
2013-08-19 14:39   ` Peter Zijlstra [this message]
2013-09-02  7:41 ` [tip:perf/core] perf/x86: " tip-bot for Yan, Zheng

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