From: Andi Kleen <ak@linux.intel.com>
To: Vince Weaver <vince@deater.net>
Cc: Andi Kleen <andi@firstfloor.org>,
mingo@elte.hu, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2
Date: Tue, 3 Sep 2013 13:28:44 -0700 [thread overview]
Message-ID: <20130903202844.GK16724@tassilo.jf.intel.com> (raw)
In-Reply-To: <alpine.DEB.2.02.1309031519440.12014@pianoman.cluster.toy>
> > + PERF_SAMPLE_BRANCH_ABORT_TX = 1U << 7, /* transaction aborts */
> > + PERF_SAMPLE_BRANCH_IN_TX = 1U << 8, /* in transaction */
> > + PERF_SAMPLE_BRANCH_NO_TX = 1U << 9, /* not in transaction */
>
> so if you specify these flags in branch_sample_type, what information
> appears in the branch record?
This is just a filter, so when set branches that do not satisfy
the filter are not reported.
The patches to export the new fields haven't been merged yet.
>
> If you get an abort, what address appears in the record?
Abort is a jump from the abort point to the abort handler or
the HLE XACQUIRE lock instruction.
> What does it mean in regards to a branch entry to be or not be in a
> transaction?
When the branch is executed the CPU is in the transactional execution
state.
>
> If you set "in transaction" does that then only record branches that are
> in transactions?
Yes, like all the other branch filter flags.
> What happens if you set both in transaction and not in?
Then you get all branches.
>
> Is there some sort of document from intel you can link to that describes
> all of this?
http://download.intel.com/products/processor/manual/253669.pdf
Chapter 17.8
-Andi
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2013-09-03 20:28 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-04-20 19:06 Basic perf PMU support for Haswell v11 Andi Kleen
2013-04-20 19:06 ` [PATCH 1/5] perf, x86: Add Haswell PEBS record support v5 Andi Kleen
2013-04-20 19:06 ` [PATCH 2/5] perf, x86: Basic Haswell PMU support v8 Andi Kleen
2013-04-20 19:06 ` [PATCH 3/5] perf, x86: Basic Haswell PEBS support v4 Andi Kleen
2013-04-20 19:06 ` [PATCH 4/5] perf, x86: Move NMI clearing to end of PMI handler after the counter registers are reset Andi Kleen
2013-04-20 19:06 ` [PATCH 5/5] perf, x86: Support Haswell v4 LBR format v2 Andi Kleen
2013-09-03 19:25 ` Vince Weaver
2013-09-03 20:28 ` Andi Kleen [this message]
2013-09-03 21:14 ` Vince Weaver
2013-09-03 22:37 ` Andi Kleen
2013-09-04 14:21 ` Vince Weaver
2013-09-04 17:05 ` Andi Kleen
2013-04-26 6:55 ` Basic perf PMU support for Haswell v11 Ingo Molnar
2013-04-26 6:59 ` Ingo Molnar
2013-05-01 10:48 ` Ingo Molnar
2013-04-26 22:52 ` Andi Kleen
2013-05-01 10:10 ` Your action on perf bug report is requested was " Andi Kleen
2013-05-01 10:33 ` Ingo Molnar
2013-05-02 8:38 ` Ingo Molnar
2013-05-02 8:49 ` Ingo Molnar
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