From: Lee Jones <lee.jones@linaro.org>
To: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Zubair Lutfullah <zubair.lutfullah@gmail.com>,
sameo@linux.intel.com, linux-kernel@vger.kernel.org,
gregkh@linuxfoundation.org
Subject: Re: [PATCH] mfd: ti_am335x_tscadc: fix spin lock and reg_cache
Date: Tue, 22 Oct 2013 17:05:23 +0100 [thread overview]
Message-ID: <20131022160523.GB24024@lee--X1> (raw)
In-Reply-To: <52667A6C.6000301@linutronix.de>
On Tue, 22 Oct 2013, Sebastian Andrzej Siewior wrote:
> On 08/07/2013 10:40 AM, Lee Jones wrote:
> > On Mon, 05 Aug 2013, Zubair Lutfullah wrote:
> >
> >> Reg_cache variable is used to lock step enable register
> >> from being accessed and written by both TSC and ADC
> >> at the same time.
> >> However, it isn't updated anywhere in the code at all.
> >>
> >> If both TSC and ADC are used, eventually 1FFFF is always
> >> written enabling all 16 steps uselessly causing a mess.
> >>
> >> Patch fixes it by correcting the locks and updates the
> >> variable by reading the step enable register
> >>
> >> Signed-off-by: Zubair Lutfullah <zubair.lutfullah@gmail.com>
> >> ---
> >> drivers/mfd/ti_am335x_tscadc.c | 4 ++--
> >> 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > Better that it comes from somewhere.
>
> I don't understand. All three functions are used before the patch has
> been applied:
>
> $ git grep -l am335x_tsc_se_set
> drivers/iio/adc/ti_am335x_adc.c
> drivers/input/touchscreen/ti_am335x_tsc.c
> drivers/mfd/ti_am335x_tscadc.c
>
> $ git grep -l am335x_tsc_se_clr
> drivers/iio/adc/ti_am335x_adc.c
> drivers/input/touchscreen/ti_am335x_tsc.c
> drivers/mfd/ti_am335x_tscadc.c
>
> $ git grep -l am335x_tsc_se_update
> drivers/iio/adc/ti_am335x_adc.c
> drivers/input/touchscreen/ti_am335x_tsc.c
> drivers/mfd/ti_am335x_tscadc.c
> include/linux/mfd/ti_am335x_tscadc.h
>
> It has been initialized to 0 by time the mfd part was loaded and
> updated via …_set() from both parts (TSC & ADC). The lock ensured that
> we never lose or add bits due to a race. So I don't understand why we
> end up with 0x1FFFF.
> Could some please explain to me how this can happen?
>
> I added reg_se_cache to cache the content of REG_SE once and
> synchronize it among TSC & ADC access. REG_SE is set to 0 by the HW
> after "work" has been done. So you need to know the old value or TSC may
> disable ADC and the other way around.
Yep, it's initialised as '0'.
12.5.1.15 STEPENABLE Register (offset = 54h) [reset = 0h]
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
next prev parent reply other threads:[~2013-10-22 16:05 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-05 19:10 Zubair Lutfullah
2013-08-07 8:40 ` Lee Jones
2013-10-22 13:15 ` Sebastian Andrzej Siewior
2013-10-22 15:48 ` Lee Jones
2013-10-22 16:28 ` Sebastian Andrzej Siewior
2013-10-25 15:53 ` Zubair Lutfullah :
2013-10-22 16:05 ` Lee Jones [this message]
2013-10-22 16:38 ` Sebastian Andrzej Siewior
2013-10-22 17:06 ` Lee Jones
2013-10-22 17:17 ` Sebastian Andrzej Siewior
2013-10-22 17:36 ` Lee Jones
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