From: Andi Kleen <ak@linux.intel.com>
To: Stephane Eranian <eranian@google.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
"Yan, Zheng" <zheng.z.yan@intel.com>,
LKML <linux-kernel@vger.kernel.org>,
"mingo@elte.hu" <mingo@elte.hu>
Subject: Re: [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold
Date: Wed, 28 May 2014 10:12:43 -0700 [thread overview]
Message-ID: <20140528171243.GL29957@tassilo.jf.intel.com> (raw)
In-Reply-To: <CABPqkBRBB0feNceYJCU43efOfyQqAugzaWzz04mr7mzEoJGhsw@mail.gmail.com>
> So, you're telling me this is a sanity check. That p->status can
> only have one bit set. Somehow that's not how I recall it working.
It can have multiple bits set. We don't know for sure for which
it is, but we should only deliver it for one anyways.
> The point is that a single PEBS record is enough for multiple
> events when the overflows occur simultaneously because they
> all get the same machine state which is correct. A single entry
> also saves space in the buffer.
The CPU will generate multiple PEBS records in this case.
So if we delivered it for all you would overcount by factor 4x
[Again this is a very unlikely situation. Normally counters
are not in lock step]
-Andi
--
ak@linux.intel.com -- Speaking for myself only
next prev parent reply other threads:[~2014-05-28 17:15 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-28 6:18 [RFC PATCH 0/7] " Yan, Zheng
2014-05-28 6:18 ` [RFC PATCH 1/7] perf, core: Add all PMUs to pmu_idr Yan, Zheng
2014-05-28 6:59 ` Peter Zijlstra
2014-05-28 6:18 ` [RFC PATCH 2/7] perf, core: introduce pmu context switch callback Yan, Zheng
2014-05-28 6:18 ` [RFC PATCH 3/7] perf, x86: use context switch callback to flush LBR stack Yan, Zheng
2014-05-28 6:18 ` [RFC PATCH 4/7] tools, perf: Allow the user to disable time stamps Yan, Zheng
2014-05-28 6:18 ` [RFC PATCH 5/7] perf, x86: use the PEBS auto reload mechanism when possible Yan, Zheng
2014-05-28 7:59 ` Peter Zijlstra
2014-05-28 14:46 ` Andi Kleen
2014-05-28 15:36 ` Peter Zijlstra
2014-05-28 6:18 ` [RFC PATCH 6/7] perf, x86: large PEBS interrupt threshold Yan, Zheng
2014-05-28 8:10 ` Peter Zijlstra
2014-05-28 12:54 ` Stephane Eranian
2014-05-28 15:02 ` Peter Zijlstra
2014-05-28 14:58 ` Andi Kleen
2014-05-28 15:24 ` Stephane Eranian
2014-05-28 16:51 ` Andi Kleen
2014-05-28 17:05 ` Stephane Eranian
2014-05-28 17:10 ` Peter Zijlstra
2014-05-28 17:12 ` Andi Kleen [this message]
2014-05-28 17:19 ` Peter Zijlstra
2014-05-28 17:45 ` Andi Kleen
2014-05-28 17:49 ` Peter Zijlstra
2014-05-28 17:09 ` Peter Zijlstra
2014-05-28 15:35 ` Peter Zijlstra
2014-05-28 16:08 ` Andi Kleen
2014-05-28 17:05 ` Peter Zijlstra
2014-05-28 17:25 ` Andi Kleen
2014-05-28 17:40 ` Stephane Eranian
2014-05-28 17:47 ` Andi Kleen
2014-05-28 19:28 ` Peter Zijlstra
2014-05-28 6:18 ` [RFC PATCH 7/7] perf, x86: drain PEBS buffer during context switch Yan, Zheng
2014-05-28 8:12 ` Peter Zijlstra
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