[Question] is it a race condition in acking PMIC sub-interrupt?

[Question] is it a race condition in acking PMIC sub-interrupt?

[Yi Zhang]

Hi, Mark:

Sorry to trouble you, I met a question related the interrupt ack
sequence in regmap framework; could you please share your advice on
this? thank you very much;

1) the following is the connection related to PMIC on my development board:

     PMIC ---> GPIO --> GIC

     the GPIO is edge triggered interrupt controller, while GIC is
level triggered;
2)  there are several interrupt ack registers in PMIC; in
regmap_irq_thread(), we acked them one by one; but if before we finish
acking all the registers, another interrupt on the "has-been-acked
register" is triggered, the interrupt line will be pulled up or down,
in the 1) case, because GPIO is edge triggered, it cannot "see" this
interrupt, then GIC cannot know either; while in regmap_irq_thread(),
the software thinks it has acked all the interrupt, then goes on; but
actually the interrupt is missed and cannot be resumed in the 1)
scenario;

Please point out what I'm wrong; thanks;

So if this is true, what about using the following methods to fix it?
a) disable all the interrupts just before ack, then enable them after
ack finished; the cons are a) the interrupt is ignored in the process;
b) we need to manipulate the registers more frequently, after all, I2C
is a slow bus;
b) polling until the interrupts are acked; but I think it's hard to
guarantee that because the interrupt is asynchronous;

and one more question:
Seems we shouldn't connect an interrupt controller as PMIC with an
edge triggered interrupt controller? Could you please share your
opinion? we can modify the hardware connection accordingly;

thank you very much; :)

Re: [Question] is it a race condition in acking PMIC sub-interrupt?

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 2016 bytes --]

On Thu, Jun 19, 2014 at 08:34:12PM +0800, Yi Zhang wrote:

> 2)  there are several interrupt ack registers in PMIC; in
> regmap_irq_thread(), we acked them one by one; but if before we finish
> acking all the registers, another interrupt on the "has-been-acked
> register" is triggered, the interrupt line will be pulled up or down,
> in the 1) case, because GPIO is edge triggered, it cannot "see" this
> interrupt, then GIC cannot know either; while in regmap_irq_thread(),
> the software thinks it has acked all the interrupt, then goes on; but
> actually the interrupt is missed and cannot be resumed in the 1)
> scenario;

You really shouldn't be using an edge triggered interrupt controller in
an application like this.

> So if this is true, what about using the following methods to fix it?
> a) disable all the interrupts just before ack, then enable them after
> ack finished; the cons are a) the interrupt is ignored in the process;
> b) we need to manipulate the registers more frequently, after all, I2C
> is a slow bus;
> b) polling until the interrupts are acked; but I think it's hard to
> guarantee that because the interrupt is asynchronous;

Right.  If the edge triggered controller is getting a level triggered
signal (which sounds like the case) then what you can probably do here
is wrap the main interrupt loop with code that checks the state of the
GPIO directly and re-calls the interrupt if it's still asserted when the
interrupt finishes.  wm8994 has some workaround code for a situation
that sounds very like yours.  If it's just getting a pulse you're in
trouble here and you have to poll but like you say it's hard to
guarantee.

> and one more question:
> Seems we shouldn't connect an interrupt controller as PMIC with an
> edge triggered interrupt controller? Could you please share your
> opinion? we can modify the hardware connection accordingly;

That's definitely the best option, muxing multiple interrupts is much
simpler and more reliable when everything is level triggered.

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]