[patch] perf: use proper dTLB-load-misses event on Ivybridge

[patch] perf: use proper dTLB-load-misses event on Ivybridge

[Vince Weaver]

This was discussed back in February 
	https://lkml.org/lkml/2014/2/18/956
But I never saw a patch come out of it.

On Ivybridge we share the Sandybridge cache event tables, but the
dTLB-load-miss event is not compatible.  Patch it up after
the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index adb02aa..f5784f0 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2465,6 +2465,9 @@ __init int intel_pmu_init(void)
 	case 62: /* IvyBridge EP */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
+		/* dTLB-load-misses on IVB is different than SNB */
+		hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
+
 		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
 		       sizeof(hw_cache_extra_regs));
 

Re: [patch] perf: use proper dTLB-load-misses event on Ivybridge

[Andi Kleen]

On Mon, Jul 14, 2014 at 03:33:25PM -0400, Vince Weaver wrote:
> 
> This was discussed back in February 
> 	https://lkml.org/lkml/2014/2/18/956
> But I never saw a patch come out of it.
> 
> On Ivybridge we share the Sandybridge cache event tables, but the
> dTLB-load-miss event is not compatible.  Patch it up after
> the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK

There is much more wrong. I've been working on revamping the whole
tables.

-Andi

Re: [patch] perf: use proper dTLB-load-misses event on Ivybridge

[Vince Weaver]

On Mon, 14 Jul 2014, Andi Kleen wrote:

> On Mon, Jul 14, 2014 at 03:33:25PM -0400, Vince Weaver wrote:
> > 
> > This was discussed back in February 
> > 	https://lkml.org/lkml/2014/2/18/956
> > But I never saw a patch come out of it.
> > 
> > On Ivybridge we share the Sandybridge cache event tables, but the
> > dTLB-load-miss event is not compatible.  Patch it up after
> > the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK
> 
> There is much more wrong. I've been working on revamping the whole
> tables.

any ETA on that?

The whole concept of generic events making life easier for casual users 
goes out the window if we're going to let them run experiments with bogus 
events.

If the IVB events are wrong we should just zero them out and give ENOENT 
for the entire lot of them rather than pretend like the kernel has useful 
event definitions.

Vince

[tip:perf/urgent] perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge

[tip-bot for Vince Weaver]

Commit-ID:  1996388e9f4e3444db8273bc08d25164d2967c21
Gitweb:     http://git.kernel.org/tip/1996388e9f4e3444db8273bc08d25164d2967c21
Author:     Vince Weaver <vincent.weaver@maine.edu>
AuthorDate: Mon, 14 Jul 2014 15:33:25 -0400
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 16 Jul 2014 13:18:40 +0200

perf/x86/intel: Use proper dTLB-load-misses event on IvyBridge

This was discussed back in February:

	https://lkml.org/lkml/2014/2/18/956

But I never saw a patch come out of it.

On IvyBridge we share the SandyBridge cache event tables, but the
dTLB-load-miss event is not compatible.  Patch it up after
the fact to the proper DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK

Signed-off-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Cc: Arnaldo Carvalho de Melo <acme@kernel.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Link: http://lkml.kernel.org/r/alpine.DEB.2.11.1407141528200.17214@vincent-weaver-1.umelst.maine.edu
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/kernel/cpu/perf_event_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 07846d7..c206815 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2474,6 +2474,9 @@ __init int intel_pmu_init(void)
 	case 62: /* IvyBridge EP */
 		memcpy(hw_cache_event_ids, snb_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
+		/* dTLB-load-misses on IVB is different than SNB */
+		hw_cache_event_ids[C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = 0x8108; /* DTLB_LOAD_MISSES.DEMAND_LD_MISS_CAUSES_A_WALK */
+
 		memcpy(hw_cache_extra_regs, snb_hw_cache_extra_regs,
 		       sizeof(hw_cache_extra_regs));