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From: Mukesh Rathor <mukesh.rathor@oracle.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>,
	boris.ostrovsky@oracle.com, david.vrabel@citrix.com,
	xen-devel@lists.xenproject.org, linux-kernel@vger.kernel.org
Subject: Re: [Xen-devel] [V0 PATCH 1/2] AMD-PVH: set EFER.NX and EFER.SCE for the boot vcpu
Date: Fri, 22 Aug 2014 12:09:27 -0700	[thread overview]
Message-ID: <20140822120927.03752bc6@mantra.us.oracle.com> (raw)
In-Reply-To: <20140822044140.GB11381@nazgul.tnic>

On Fri, 22 Aug 2014 06:41:40 +0200
Borislav Petkov <bp@alien8.de> wrote:

> On Thu, Aug 21, 2014 at 07:46:56PM -0700, Mukesh Rathor wrote:
> > Intel doesn't have EFER.NX bit.
> 
> Of course it does.
> 

Right, it does. Some code/comment is misleading... Anyways, reading
intel SDMs, if I understand the convoluted text correctly, EFER.NX is
not required to be set for l1.nx to be set, thus allowing for page
level protection. Where as on AMD, EFER.NX must be set for l1.nx to
be used. So, in the end, this patch would apply to both amd/intel.... 

I'll reword and submit.

Thanks,
Mukesh


  reply	other threads:[~2014-08-22 19:09 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-08-21  2:16 [V0 PATCH 0/2] AMD PVH domU support Mukesh Rathor
2014-08-21  2:16 ` [V0 PATCH 1/2] AMD-PVH: set EFER.NX and EFER.SCE for the boot vcpu Mukesh Rathor
2014-08-22  1:39   ` [Xen-devel] " Konrad Rzeszutek Wilk
2014-08-22  2:46     ` Mukesh Rathor
2014-08-22  3:32       ` Konrad Rzeszutek Wilk
2014-08-22  4:41       ` Borislav Petkov
2014-08-22 19:09         ` Mukesh Rathor [this message]
2014-08-22 23:29           ` Mukesh Rathor
2014-08-21  2:16 ` [V0 PATCH 2/2] AMD-PVH: set EFER.NX and EFER.SCE for secondary vcpus Mukesh Rathor
2014-08-22 13:52 ` [V0 PATCH 0/2] AMD PVH domU support David Vrabel
2014-08-22 13:55   ` David Vrabel
2014-08-22 19:15     ` Mukesh Rathor
2014-08-22 22:20   ` Mukesh Rathor

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