From: Catalin Marinas <catalin.marinas@arm.com>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Will Deacon <Will.Deacon@arm.com>,
Peter Zijlstra <peterz@infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Russell King - ARM Linux <linux@arm.linux.org.uk>,
Benjamin Herrenschmidt <benh@kernel.crashing.org>
Subject: Re: [RFC PATCH 1/2] zap_pte_range: update addr when forcing flush after TLB batching faiure
Date: Thu, 6 Nov 2014 13:57:40 +0000 [thread overview]
Message-ID: <20141106135740.GC19702@e104818-lin.cambridge.arm.com> (raw)
In-Reply-To: <CA+55aFzBggoXtNXQeng5d_mRoDnaMBE5Y+URs+PHR67nUpMtaw@mail.gmail.com>
On Tue, Nov 04, 2014 at 04:08:27PM +0000, Linus Torvalds wrote:
> On Tue, Nov 4, 2014 at 6:29 AM, Catalin Marinas <catalin.marinas@arm.com> wrote:
> >
> > This would work on arm64 but is the PAGE_SIZE range enough for all
> > architectures even when we flush a huge page or a pmd/pud table entry?
>
> It pretty much had *better* be.
Thanks for confirming.
> For things like page tables caches (ie caching addresses "inside" the
> page tables, like x86 does), for legacy reasons, flushing an
> individual page had better flush the page table caches behind it. This
> is definitely how x86 works, for example. And if you have an
> architected non-legacy page table cache (which I'm not aware of
> anybody actually doing), you're going to have some architecturally
> explicit flushing for that, likely *separate* from a regular TLB entry
> flush, and thus you'd need more than just some range expansion..
On arm64 we have two types of TLB invalidation instructions, the
standard one which flushes a pte entry together with the corresponding
upper level page table cache and a "leaf" operation only for the pte. We
don't use the latter in Linux (yet) but in theory it's more efficient.
Anyway, even without special "leaf" operations, it would be useful to
make the distinction between unmap_vmas() and free_pgtables() with
regards to the ranges tracked by mmu_gather. For the former, tlb_flush()
needs to flush the range in PAGE_SIZE increments (assuming a mix of
small and huge pages). For the latter, PMD_SIZE increments would be
enough.
With RCU_TABLE_FREE, I think checking tlb->local.next would do the trick
but for x86 we can keep mmu_gather.need_flush only for pte clearing
and remove need_flush = 1 from p*_free_tlb() functions. The arch
specific tlb_flush() can take need_flush into account to change the
range flushing increment or even ignore the second tlb_flush() triggered
by tlb_finish_mmu() (after free_pgtables(), the ptes have been flushed
via tlb_end_vma()).
--
Catalin
next prev parent reply other threads:[~2014-11-06 13:57 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-10-28 11:44 [RFC PATCH 0/2] Fix a couple of issues with zap_pte_range and MMU gather Will Deacon
2014-10-28 11:44 ` [RFC PATCH 1/2] zap_pte_range: update addr when forcing flush after TLB batching faiure Will Deacon
2014-10-28 15:30 ` Linus Torvalds
2014-10-28 16:07 ` Will Deacon
2014-10-28 16:25 ` Linus Torvalds
2014-10-28 17:07 ` Will Deacon
2014-10-28 18:03 ` Linus Torvalds
2014-10-28 21:16 ` Benjamin Herrenschmidt
2014-10-28 21:32 ` Linus Torvalds
2014-10-28 21:40 ` Linus Torvalds
2014-10-29 19:47 ` Will Deacon
2014-10-29 21:11 ` Linus Torvalds
2014-10-29 21:27 ` Benjamin Herrenschmidt
2014-11-01 17:01 ` Linus Torvalds
2014-11-01 20:25 ` Benjamin Herrenschmidt
2014-11-03 17:56 ` Will Deacon
2014-11-03 18:05 ` Linus Torvalds
2014-11-04 14:29 ` Catalin Marinas
2014-11-04 16:08 ` Linus Torvalds
2014-11-06 13:57 ` Catalin Marinas [this message]
2014-11-06 17:53 ` Linus Torvalds
2014-11-06 18:38 ` Catalin Marinas
2014-11-06 21:29 ` Linus Torvalds
2014-11-07 16:50 ` Catalin Marinas
2014-11-10 13:56 ` Will Deacon
2014-10-28 11:44 ` [RFC PATCH 2/2] zap_pte_range: fix partial TLB flushing in response to a dirty pte Will Deacon
2014-10-28 15:18 ` Linus Torvalds
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