From: Mark Brown <broonie@kernel.org>
To: Alexander Stein <alexander.stein@systec-electronic.com>
Cc: linux-kernel@vger.kernel.org
Subject: Re: regmap: mmio: regression in pre-v4.6-rc1
Date: Wed, 23 Mar 2016 11:39:39 +0000 [thread overview]
Message-ID: <20160323113939.GI2566@sirena.org.uk> (raw)
In-Reply-To: <4116114.XWfjkrStv7@ws-stein>
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On Wed, Mar 23, 2016 at 12:16:13PM +0100, Alexander Stein wrote:
> On Wednesday 23 March 2016 10:34:15, Mark Brown wrote:
> > Are you *sure* that this is actually big endian? Are you basing this on
> > documentation or on what happened to work for you in the past.
> Please refer to QorIQ LS1021A Reference Manual (REV 0) table 2.2 (CCSR block
> base address map) which states that this peripheral (among _most_ but not all)
> requires byte swapping. Same for DSPI.
> Yeah, it sounds strange.
I don't have that document.
> > Have you tried tracing through the code to see what ends up happening to
> > the I/O? It should come out using your architecture's big endian
> > accessors.
> In regmap_mmio_gen_context ctx->reg_read is set to regmap_mmio_read32le and
> ctx->reg_write to regmap_mmio_write32le respectively.
So how does that happen then? We set these values if the bus is
default, little or native endian but if it's big endian we go into a
completely different case...
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next prev parent reply other threads:[~2016-03-23 11:39 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-03-23 8:48 Alexander Stein
2016-03-23 9:43 ` Alexander Stein
2016-03-23 10:34 ` Mark Brown
2016-03-23 11:16 ` Alexander Stein
2016-03-23 11:39 ` Mark Brown [this message]
2016-03-23 11:50 ` Alexander Stein
2016-03-23 12:05 ` Mark Brown
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