From: Dave Hansen <dave@sr71.net>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Dave Hansen <dave@sr71.net>,
dave.hansen@linux.intel.com, luto@kernel.org,
peterz@infradead.org
Subject: [PATCH 05/20] x86, msr: use Intel family macros for msr events code
Date: Wed, 01 Jun 2016 17:12:04 -0700 [thread overview]
Message-ID: <20160602001204.280093E6@viggo.jf.intel.com> (raw)
In-Reply-To: <20160602001157.D8BE59D7@viggo.jf.intel.com>
From: Dave Hansen <dave.hansen@linux.intel.com>
Use the new INTEL_FAM6_MODEL_* macros for arch/x86/events/msr.c.
This code appears to be missing handling for "WESTMERE2" and
"SKYLAKE_X".
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
---
b/arch/x86/events/msr.c | 59 ++++++++++++++++++++++++------------------------
1 file changed, 30 insertions(+), 29 deletions(-)
diff -puN arch/x86/events/msr.c~x86-intel-familites-msr arch/x86/events/msr.c
--- a/arch/x86/events/msr.c~x86-intel-familites-msr 2016-06-01 15:45:04.638964953 -0700
+++ b/arch/x86/events/msr.c 2016-06-01 15:45:04.643965181 -0700
@@ -1,4 +1,5 @@
#include <linux/perf_event.h>
+#include <asm/intel-family.h>
enum perf_msr_id {
PERF_MSR_TSC = 0,
@@ -34,39 +35,39 @@ static bool test_intel(int idx)
return false;
switch (boot_cpu_data.x86_model) {
- case 30: /* 45nm Nehalem */
- case 26: /* 45nm Nehalem-EP */
- case 46: /* 45nm Nehalem-EX */
-
- case 37: /* 32nm Westmere */
- case 44: /* 32nm Westmere-EP */
- case 47: /* 32nm Westmere-EX */
-
- case 42: /* 32nm SandyBridge */
- case 45: /* 32nm SandyBridge-E/EN/EP */
-
- case 58: /* 22nm IvyBridge */
- case 62: /* 22nm IvyBridge-EP/EX */
-
- case 60: /* 22nm Haswell Core */
- case 63: /* 22nm Haswell Server */
- case 69: /* 22nm Haswell ULT */
- case 70: /* 22nm Haswell + GT3e (Intel Iris Pro graphics) */
-
- case 61: /* 14nm Broadwell Core-M */
- case 86: /* 14nm Broadwell Xeon D */
- case 71: /* 14nm Broadwell + GT3e (Intel Iris Pro graphics) */
- case 79: /* 14nm Broadwell Server */
-
- case 55: /* 22nm Atom "Silvermont" */
- case 77: /* 22nm Atom "Silvermont Avoton/Rangely" */
- case 76: /* 14nm Atom "Airmont" */
+ case INTEL_FAM6_MODEL_NEHALEM:
+ case INTEL_FAM6_MODEL_NEHALEM_EP:
+ case INTEL_FAM6_MODEL_NEHALEM_EX:
+
+ case INTEL_FAM6_MODEL_WESTMERE:
+ case INTEL_FAM6_MODEL_WESTMERE_EP:
+ case INTEL_FAM6_MODEL_WESTMERE_EX:
+
+ case INTEL_FAM6_MODEL_SANDYBRIDGE:
+ case INTEL_FAM6_MODEL_SANDYBRIDGE_X:
+
+ case INTEL_FAM6_MODEL_IVYBRIDGE:
+ case INTEL_FAM6_MODEL_IVYBRIDGE_X:
+
+ case INTEL_FAM6_MODEL_HASWELL_CORE:
+ case INTEL_FAM6_MODEL_HASWELL_X:
+ case INTEL_FAM6_MODEL_HASWELL_ULT:
+ case INTEL_FAM6_MODEL_HASWELL_GT3E:
+
+ case INTEL_FAM6_MODEL_BROADWELL_CORE_M:
+ case INTEL_FAM6_MODEL_BROADWELL_XEON_D:
+ case INTEL_FAM6_MODEL_BROADWELL_GT3E:
+ case INTEL_FAM6_MODEL_BROADWELL_X:
+
+ case INTEL_FAM6_MODEL_ATOM_SILVERMONT1:
+ case INTEL_FAM6_MODEL_ATOM_SILVERMONT2:
+ case INTEL_FAM6_MODEL_ATOM_AIRMONT:
if (idx == PERF_MSR_SMI)
return true;
break;
- case 78: /* 14nm Skylake Mobile */
- case 94: /* 14nm Skylake Desktop */
+ case INTEL_FAM6_MODEL_SKYLAKE_MOBILE:
+ case INTEL_FAM6_MODEL_SKYLAKE_DESKTOP:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
_
next prev parent reply other threads:[~2016-06-02 0:16 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 0:11 [PATCH 01/20] x86, intel: Introduce macros for Intel family numbers Dave Hansen
2016-06-02 0:12 ` [PATCH 02/20] x86, perf: use Intel family macros for core perf events Dave Hansen
2016-06-02 0:12 ` [PATCH 03/20] x86, rapl: use Intel family macros for rapl Dave Hansen
2016-06-02 0:12 ` [PATCH 04/20] x86, intel_idle: use Intel family macros for intel_idle Dave Hansen
2016-06-02 0:12 ` Dave Hansen [this message]
2016-06-02 0:12 ` [PATCH 06/20] x86, msr: add missing Intel models Dave Hansen
2016-06-02 0:12 ` [PATCH 07/20] x86, intel: use Intel model macros intead of open-coding Dave Hansen
2016-06-02 0:12 ` [PATCH 08/20] x86, rapl: reorder cpu detection table Dave Hansen
2016-06-02 0:12 ` [PATCH 09/20] x86, platform: use new Intel model number macros Dave Hansen
2016-06-02 0:12 ` [PATCH 10/20] x86, cstate: use Intel Model name macros Dave Hansen
2016-06-02 0:12 ` [PATCH 11/20] x86, uncore: use Intel family name macros for uncore Dave Hansen
2016-06-02 0:12 ` [PATCH 12/20] x86, edac: use Intel family name macros for edac driver Dave Hansen
2016-06-02 16:16 ` Luck, Tony
2016-06-02 17:27 ` Luck, Tony
2016-06-02 0:12 ` [PATCH 13/20] x86, cpufreq: use Intel family name macros for intel_pstate cpufreq driver Dave Hansen
2016-06-02 0:12 ` [PATCH 14/20] x86, acpi, lss: use Intel family name macros for lpss driver Dave Hansen
2016-06-02 0:12 ` [PATCH 15/20] x86, intel_telemetry: use Intel family name macros for telemetry driver Dave Hansen
2016-06-02 0:12 ` [PATCH 16/20] x86, pmc_core: use Intel family name macros for pmc_core driver Dave Hansen
2016-06-02 0:12 ` [PATCH 17/20] x86, mmc: use Intel family name macros for mmc driver Dave Hansen
2016-06-02 6:08 ` Adrian Hunter
2016-06-03 7:42 ` Ulf Hansson
2016-06-02 0:12 ` [PATCH 18/20] x86, thermal: clean up and fix cpu model detection for intel_soc_dts_thermal Dave Hansen
2016-06-02 0:12 ` [PATCH 19/20] x86, rapl: add Skylake server model detection Dave Hansen
2016-06-02 0:12 ` [PATCH 20/20] x86, powercap, rapl: add Skylake Server model number Dave Hansen
2016-06-02 6:57 ` [PATCH 01/20] x86, intel: Introduce macros for Intel family numbers Borislav Petkov
2016-06-02 21:49 ` Rafael J. Wysocki
2016-06-02 21:45 ` Darren Hart
2016-06-03 0:19 [PATCH 01/20] [v2] " Dave Hansen
2016-06-03 0:19 ` [PATCH 05/20] x86, msr: use Intel family macros for msr events code Dave Hansen
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