From: Dave Hansen <dave@sr71.net>
To: linux-kernel@vger.kernel.org
Cc: x86@kernel.org, Dave Hansen <dave@sr71.net>,
dave.hansen@linux.intel.com, tglx@linutronix.de,
kan.liang@intel.com
Subject: [PATCH 10/20] x86, cstate: use Intel Model name macros
Date: Wed, 01 Jun 2016 17:12:11 -0700 [thread overview]
Message-ID: <20160602001211.D6BE174E@viggo.jf.intel.com> (raw)
In-Reply-To: <20160602001157.D8BE59D7@viggo.jf.intel.com>
From: Dave Hansen <dave.hansen@linux.intel.com>
This should be getting old by now. Use the new macros intead of
open-coded magic numbers.
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Kan Liang <kan.liang@intel.com>
---
b/arch/x86/events/intel/cstate.c | 47 +++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 23 deletions(-)
diff -puN arch/x86/events/intel/cstate.c~x86-intel-familites-cstate arch/x86/events/intel/cstate.c
--- a/arch/x86/events/intel/cstate.c~x86-intel-familites-cstate 2016-06-01 15:45:06.804063686 -0700
+++ b/arch/x86/events/intel/cstate.c 2016-06-01 15:45:06.807063823 -0700
@@ -89,6 +89,7 @@
#include <linux/slab.h>
#include <linux/perf_event.h>
#include <asm/cpu_device_id.h>
+#include <asm/intel-family.h>
#include "../perf_event.h"
MODULE_LICENSE("GPL");
@@ -511,37 +512,37 @@ static const struct cstate_model slm_cst
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long) &(states) }
static const struct x86_cpu_id intel_cstates_match[] __initconst = {
- X86_CSTATES_MODEL(30, nhm_cstates), /* 45nm Nehalem */
- X86_CSTATES_MODEL(26, nhm_cstates), /* 45nm Nehalem-EP */
- X86_CSTATES_MODEL(46, nhm_cstates), /* 45nm Nehalem-EX */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_NEHALEM, nhm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_NEHALEM_EP, nhm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_NEHALEM_EX, nhm_cstates),
- X86_CSTATES_MODEL(37, nhm_cstates), /* 32nm Westmere */
- X86_CSTATES_MODEL(44, nhm_cstates), /* 32nm Westmere-EP */
- X86_CSTATES_MODEL(47, nhm_cstates), /* 32nm Westmere-EX */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_WESTMERE, nhm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_WESTMERE_EP, nhm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_WESTMERE_EX, nhm_cstates),
- X86_CSTATES_MODEL(42, snb_cstates), /* 32nm SandyBridge */
- X86_CSTATES_MODEL(45, snb_cstates), /* 32nm SandyBridge-E/EN/EP */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SANDYBRIDGE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SANDYBRIDGE_X, snb_cstates),
- X86_CSTATES_MODEL(58, snb_cstates), /* 22nm IvyBridge */
- X86_CSTATES_MODEL(62, snb_cstates), /* 22nm IvyBridge-EP/EX */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_IVYBRIDGE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_IVYBRIDGE_X, snb_cstates),
- X86_CSTATES_MODEL(60, snb_cstates), /* 22nm Haswell Core */
- X86_CSTATES_MODEL(63, snb_cstates), /* 22nm Haswell Server */
- X86_CSTATES_MODEL(70, snb_cstates), /* 22nm Haswell + GT3e */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_CORE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_X, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_GT3E, snb_cstates),
- X86_CSTATES_MODEL(69, hswult_cstates), /* 22nm Haswell ULT */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_HASWELL_ULT, hswult_cstates),
- X86_CSTATES_MODEL(55, slm_cstates), /* 22nm Atom Silvermont */
- X86_CSTATES_MODEL(77, slm_cstates), /* 22nm Atom Avoton/Rangely */
- X86_CSTATES_MODEL(76, slm_cstates), /* 22nm Atom Airmont */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_ATOM_SILVERMONT1, slm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_ATOM_SILVERMONT2, slm_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_ATOM_AIRMONT, slm_cstates),
- X86_CSTATES_MODEL(61, snb_cstates), /* 14nm Broadwell Core-M */
- X86_CSTATES_MODEL(86, snb_cstates), /* 14nm Broadwell Xeon D */
- X86_CSTATES_MODEL(71, snb_cstates), /* 14nm Broadwell + GT3e */
- X86_CSTATES_MODEL(79, snb_cstates), /* 14nm Broadwell Server */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_CORE_M, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_XEON_D, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_GT3E, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_BROADWELL_X, snb_cstates),
- X86_CSTATES_MODEL(78, snb_cstates), /* 14nm Skylake Mobile */
- X86_CSTATES_MODEL(94, snb_cstates), /* 14nm Skylake Desktop */
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SKYLAKE_MOBILE, snb_cstates),
+ X86_CSTATES_MODEL(INTEL_FAM6_MODEL_SKYLAKE_DESKTOP, snb_cstates),
{ },
};
MODULE_DEVICE_TABLE(x86cpu, intel_cstates_match);
_
next prev parent reply other threads:[~2016-06-02 0:12 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-02 0:11 [PATCH 01/20] x86, intel: Introduce macros for Intel family numbers Dave Hansen
2016-06-02 0:12 ` [PATCH 02/20] x86, perf: use Intel family macros for core perf events Dave Hansen
2016-06-02 0:12 ` [PATCH 03/20] x86, rapl: use Intel family macros for rapl Dave Hansen
2016-06-02 0:12 ` [PATCH 04/20] x86, intel_idle: use Intel family macros for intel_idle Dave Hansen
2016-06-02 0:12 ` [PATCH 05/20] x86, msr: use Intel family macros for msr events code Dave Hansen
2016-06-02 0:12 ` [PATCH 06/20] x86, msr: add missing Intel models Dave Hansen
2016-06-02 0:12 ` [PATCH 07/20] x86, intel: use Intel model macros intead of open-coding Dave Hansen
2016-06-02 0:12 ` [PATCH 08/20] x86, rapl: reorder cpu detection table Dave Hansen
2016-06-02 0:12 ` [PATCH 09/20] x86, platform: use new Intel model number macros Dave Hansen
2016-06-02 0:12 ` Dave Hansen [this message]
2016-06-02 0:12 ` [PATCH 11/20] x86, uncore: use Intel family name macros for uncore Dave Hansen
2016-06-02 0:12 ` [PATCH 12/20] x86, edac: use Intel family name macros for edac driver Dave Hansen
2016-06-02 16:16 ` Luck, Tony
2016-06-02 17:27 ` Luck, Tony
2016-06-02 0:12 ` [PATCH 13/20] x86, cpufreq: use Intel family name macros for intel_pstate cpufreq driver Dave Hansen
2016-06-02 0:12 ` [PATCH 14/20] x86, acpi, lss: use Intel family name macros for lpss driver Dave Hansen
2016-06-02 0:12 ` [PATCH 15/20] x86, intel_telemetry: use Intel family name macros for telemetry driver Dave Hansen
2016-06-02 0:12 ` [PATCH 16/20] x86, pmc_core: use Intel family name macros for pmc_core driver Dave Hansen
2016-06-02 0:12 ` [PATCH 17/20] x86, mmc: use Intel family name macros for mmc driver Dave Hansen
2016-06-02 6:08 ` Adrian Hunter
2016-06-03 7:42 ` Ulf Hansson
2016-06-02 0:12 ` [PATCH 18/20] x86, thermal: clean up and fix cpu model detection for intel_soc_dts_thermal Dave Hansen
2016-06-02 0:12 ` [PATCH 19/20] x86, rapl: add Skylake server model detection Dave Hansen
2016-06-02 0:12 ` [PATCH 20/20] x86, powercap, rapl: add Skylake Server model number Dave Hansen
2016-06-02 6:57 ` [PATCH 01/20] x86, intel: Introduce macros for Intel family numbers Borislav Petkov
2016-06-02 21:49 ` Rafael J. Wysocki
2016-06-02 21:45 ` Darren Hart
2016-06-03 0:19 [PATCH 01/20] [v2] " Dave Hansen
2016-06-03 0:19 ` [PATCH 10/20] x86, cstate: use Intel Model name macros Dave Hansen
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160602001211.D6BE174E@viggo.jf.intel.com \
--to=dave@sr71.net \
--cc=dave.hansen@linux.intel.com \
--cc=kan.liang@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®