mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
From: Guenter Roeck <linux@roeck-us.net>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: Shawn Lin <shawn.lin@rock-chips.com>,
	devicetree@vger.kernel.org, Wenrui Li <wenrui.li@rock-chips.com>,
	Heiko Stuebner <heiko@sntech.de>, Arnd Bergmann <arnd@arndb.de>,
	Marc Zyngier <marc.zyngier@arm.com>,
	linux-pci@vger.kernel.org,
	Brian Norris <briannorris@chromium.org>,
	linux-kernel@vger.kernel.org,
	Doug Anderson <dianders@chromium.org>,
	linux-rockchip@lists.infradead.org,
	Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH v2 10/15] Group related CSR definitions together.
Date: Fri, 2 Sep 2016 14:40:34 -0700	[thread overview]
Message-ID: <20160902214034.GB31011@roeck-us.net> (raw)
In-Reply-To: <20160902155518.8650.89467.stgit@bhelgaas-glaptop2.roam.corp.google.com>

On Fri, Sep 02, 2016 at 10:55:19AM -0500, Bjorn Helgaas wrote:
> 
> ---
>  drivers/pci/host/pcie-rockchip.c |  148 +++++++++++++++++++-------------------
>  1 file changed, 74 insertions(+), 74 deletions(-)
> 
> diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
> index 6edfce5..fe1b52f 100644
> --- a/drivers/pci/host/pcie-rockchip.c
> +++ b/drivers/pci/host/pcie-rockchip.c
> @@ -37,21 +37,27 @@
>  #include <linux/reset.h>
>  #include <linux/regmap.h>
>  
> -#define PCIE_CLIENT_BASE			0x0
> -#define PCIE_RC_CONFIG_BASE			0xa00000
> -#define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2	(PCIE_RC_CONFIG_BASE + 0x90c)
> -#define PCIE_RC_CONFIG_LCS			(PCIE_RC_CONFIG_BASE + 0x0d0)
> -#define  PCIE_RC_CONFIG_LCS_RETRAIN_LINK	BIT(5)
> -#define  PCIE_RC_CONFIG_LCS_LBMIE		BIT(10)
> -#define  PCIE_RC_CONFIG_LCS_LABIE		BIT(11)
> -#define  PCIE_RC_CONFIG_LCS_LBMS		BIT(30)
> -#define  PCIE_RC_CONFIG_LCS_LAMS		BIT(31)
> -#define PCIE_CORE_CTRL_MGMT_BASE		0x900000
> -#define PCIE_CORE_AXI_CONF_BASE			0xc00000
> -#define PCIE_CORE_AXI_INBOUND_BASE		0xc00800
> -#define PCIE_CLIENT_BASIC_STATUS1		(PCIE_CLIENT_BASE + 0x48)
> -#define PCIE_CLIENT_INT_MASK			(PCIE_CLIENT_BASE + 0x4c)
> -#define PCIE_CLIENT_INT_STATUS			(PCIE_CLIENT_BASE + 0x50)
> +/*
> + * The upper 16 bits of PCIE_CLIENT_BASE are a write mask for the lower 16
> + * bits.  This allows atomic updates of the register without locking.
> + */
> +#define HIWORD_UPDATE(mask, val)	((mask << 16) | val)
> +
(mask), (val)

> +#define ENCODE_LANES(x)			(((x >> 1) & 3) << 4)

(x)

Guenter

  reply	other threads:[~2016-09-02 21:40 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-02 15:53 [PATCH v2 00/15] PCI: rockchip: Cleanups against v10 Bjorn Helgaas
2016-09-02 15:53 ` [PATCH v2 01/15] Remove unused symbols, unnecessary parens, other minor comments from Bjorn Helgaas
2016-09-02 21:42   ` Guenter Roeck
2016-09-02 22:15     ` Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 02/15] Rename pcie_read() and pcie_write() to rockchip_pcie_read() and Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 03/15] Always use "rockchip" as the pointer to per-device struct Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 04/15] Rename struct rockchip_pcie_port to struct rockchip_pcie Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 05/15] Use a local "dev" to avoid repetition of "rockchip->dev" Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 06/15] Add comment about why 32-bit read/modify/write isn't safe Bjorn Helgaas
2016-09-02 15:54 ` [PATCH v2 07/15] Simplify the confusing HIWORD_UPDATE scheme Bjorn Helgaas
2016-09-02 21:38   ` Guenter Roeck
2016-09-02 22:09     ` Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 08/15] Remove duplicate CSR definition Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 09/15] Move CSR bases into definition Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 10/15] Group related CSR definitions together Bjorn Helgaas
2016-09-02 21:40   ` Guenter Roeck [this message]
2016-09-02 15:55 ` [PATCH v2 11/15] Rename PCIE_CORE_RC_CONF_SCC_SHIFT to match similar definitions Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 12/15] Rename ROCKCHIP_PCIE_RPIFR1_INTR_MASK and ROCKCHIP_PCIE_RPIFR1_INTR_SHIFT Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 13/15] The register at PCIE_CLIENT_BASE presumably has a name of its own. Add a Bjorn Helgaas
2016-09-02 15:55 ` [PATCH v2 14/15] Simplify testing of link status and speed testing Bjorn Helgaas
2016-09-02 15:56 ` [PATCH v2 15/15] Move msleeps to address Guenter's comments Bjorn Helgaas
2016-09-03  2:37 ` [PATCH v2 00/15] PCI: rockchip: Cleanups against v10 Shawn Lin
2016-09-03 16:34   ` Bjorn Helgaas
2016-09-03 17:17     ` Bjorn Helgaas

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20160902214034.GB31011@roeck-us.net \
    --to=linux@roeck-us.net \
    --cc=arnd@arndb.de \
    --cc=bhelgaas@google.com \
    --cc=briannorris@chromium.org \
    --cc=devicetree@vger.kernel.org \
    --cc=dianders@chromium.org \
    --cc=heiko@sntech.de \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-rockchip@lists.infradead.org \
    --cc=marc.zyngier@arm.com \
    --cc=robh+dt@kernel.org \
    --cc=shawn.lin@rock-chips.com \
    --cc=wenrui.li@rock-chips.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®