[PATCH v1 1/1] x86/platform/intel-mid: Implement power off sequence

[PATCH v1 1/1] x86/platform/intel-mid: Implement power off sequence

[Andy Shevchenko]

Tell SCU that we are about powering off the device.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
 arch/x86/include/asm/intel-mid.h        |  2 ++
 arch/x86/include/asm/intel_scu_ipc.h    |  2 ++
 arch/x86/platform/intel-mid/intel-mid.c |  5 +++++
 arch/x86/platform/intel-mid/pwr.c       | 27 ++++++++++++++++++++++++++-
 4 files changed, 35 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h
index 9d6b097..5b6753d 100644
--- a/arch/x86/include/asm/intel-mid.h
+++ b/arch/x86/include/asm/intel-mid.h
@@ -18,6 +18,8 @@
 extern int intel_mid_pci_init(void);
 extern int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
 
+extern void intel_mid_pwr_power_off(void);
+
 #define INTEL_MID_PWR_LSS_OFFSET	4
 #define INTEL_MID_PWR_LSS_TYPE		(1 << 7)
 
diff --git a/arch/x86/include/asm/intel_scu_ipc.h b/arch/x86/include/asm/intel_scu_ipc.h
index 925b605..4fb1d0a 100644
--- a/arch/x86/include/asm/intel_scu_ipc.h
+++ b/arch/x86/include/asm/intel_scu_ipc.h
@@ -3,6 +3,8 @@
 
 #include <linux/notifier.h>
 
+#define IPCMSG_COLD_OFF		0x80	/* Only for Tangier */
+
 #define IPCMSG_WARM_RESET	0xF0
 #define IPCMSG_COLD_RESET	0xF1
 #define IPCMSG_SOFT_RESET	0xF2
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index ce119d2..e74f3ea 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -70,6 +70,11 @@ EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip);
 
 static void intel_mid_power_off(void)
 {
+	/* Shut down South Complex via PMU */
+	intel_mid_pwr_power_off();
+
+	/* Only for Tangier, the rest will ignore this command */
+	intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1);
 };
 
 static void intel_mid_reboot(void)
diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c
index 0548741..d73e2d3 100644
--- a/arch/x86/platform/intel-mid/pwr.c
+++ b/arch/x86/platform/intel-mid/pwr.c
@@ -48,7 +48,15 @@
 #define PM_CMD_CM_IMMEDIATE	(1 << 9)
 #define PM_CMD_CM_DELAY		(2 << 9)
 #define PM_CMD_CM_TRIGGER	(3 << 9)
-#define PM_CMD_D3cold		(1 << 21)
+
+/* System states */
+#define PM_CMD_SYS_STATE_S5	(5 << 16)
+
+/* Trigger variants */
+#define PM_CMD_CFG_TRIGGER_NC	(3 << 19)
+
+/* Message to wait for TRIGGER_NC case */
+#define TRIGGER_NC_MSG_2	(2 << 22)
 
 /* List of commands */
 #define CMD_SET_CFG		0x01
@@ -264,6 +272,23 @@ int intel_mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
 }
 EXPORT_SYMBOL_GPL(intel_mid_pci_set_power_state);
 
+void intel_mid_pwr_power_off(void)
+{
+	struct mid_pwr *pwr = midpwr;
+	u8 cmd = PM_CMD_SYS_STATE_S5 |
+		 PM_CMD_CMD(CMD_SET_CFG) |
+		 PM_CMD_CM_TRIGGER |
+		 PM_CMD_CFG_TRIGGER_NC |
+		 TRIGGER_NC_MSG_2;
+
+	mid_pwr_wait(pwr);
+
+	/* Send command to SCU */
+	writel(cmd, pwr->regs + PM_CMD);
+
+	mid_pwr_wait(pwr);
+}
+
 int intel_mid_pwr_get_lss_id(struct pci_dev *pdev)
 {
 	int vndr;
-- 
2.9.3

Re: [PATCH v1 1/1] x86/platform/intel-mid: Implement power off sequence

[kbuild test robot]

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Hi Andy,

[auto build test WARNING on tip/auto-latest]
[also build test WARNING on next-20160906]
[cannot apply to tip/x86/core v4.8-rc5]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
[Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on]
[Check https://git-scm.com/docs/git-format-patch for more information]

url:    https://github.com/0day-ci/linux/commits/Andy-Shevchenko/x86-platform-intel-mid-Implement-power-off-sequence/20160907-114644
config: x86_64-randconfig-x006-201636 (attached as .config)
compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        # save the attached .config to linux build tree
        make ARCH=x86_64 

All warnings (new ones prefixed by >>):

   arch/x86/platform/intel-mid/pwr.c: In function 'intel_mid_pwr_power_off':
>> arch/x86/platform/intel-mid/pwr.c:53:29: warning: large integer implicitly truncated to unsigned type [-Woverflow]
    #define PM_CMD_SYS_STATE_S5 (5 << 16)
                                ^
>> arch/x86/platform/intel-mid/pwr.c:278:11: note: in expansion of macro 'PM_CMD_SYS_STATE_S5'
     u8 cmd = PM_CMD_SYS_STATE_S5 |
              ^~~~~~~~~~~~~~~~~~~

vim +53 arch/x86/platform/intel-mid/pwr.c

    37	#define PM_WKS(x)		(0x18 + (x) * 4)
    38	#define PM_SSC(x)		(0x20 + (x) * 4)
    39	#define PM_SSS(x)		(0x30 + (x) * 4)
    40	
    41	/* Bits in PM_STS */
    42	#define PM_STS_BUSY		(1 << 8)
    43	
    44	/* Bits in PM_CMD */
    45	#define PM_CMD_CMD(x)		((x) << 0)
    46	#define PM_CMD_IOC		(1 << 8)
    47	#define PM_CMD_CM_NOP		(0 << 9)
    48	#define PM_CMD_CM_IMMEDIATE	(1 << 9)
    49	#define PM_CMD_CM_DELAY		(2 << 9)
    50	#define PM_CMD_CM_TRIGGER	(3 << 9)
    51	
    52	/* System states */
  > 53	#define PM_CMD_SYS_STATE_S5	(5 << 16)
    54	
    55	/* Trigger variants */
    56	#define PM_CMD_CFG_TRIGGER_NC	(3 << 19)
    57	
    58	/* Message to wait for TRIGGER_NC case */
    59	#define TRIGGER_NC_MSG_2	(2 << 22)
    60	
    61	/* List of commands */

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation

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