From: Peter Zijlstra <peterz@infradead.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Bin Gao <bin.gao@linux.intel.com>, Ingo Molnar <mingo@redhat.com>,
"H. Peter Anvin" <hpa@zytor.com>,
John Stultz <john.stultz@linaro.org>,
x86@kernel.org, linux-kernel@vger.kernel.org, bin.gao@intel.com
Subject: Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag
Date: Thu, 20 Oct 2016 12:17:47 +0200 [thread overview]
Message-ID: <20161020101747.GT3102@twins.programming.kicks-ass.net> (raw)
In-Reply-To: <alpine.DEB.2.20.1610201154020.5073@nanos>
On Thu, Oct 20, 2016 at 11:57:03AM +0200, Thomas Gleixner wrote:
> On Thu, 13 Oct 2016, Bin Gao wrote:
> > @@ -702,6 +702,15 @@ unsigned long native_calibrate_tsc(void)
> > }
> > }
> >
> > + setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
> > +
> > + /*
> > + * For Atom SoCs TSC is the only reliable clocksource.
> > + * Mark TSC reliable so no watchdog on it.
> > + */
> > + if (boot_cpu_data.x86_model == INTEL_FAM6_ATOM_GOLDMONT)
> > + setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
> > +
AFAICT setting TSC_RELIABLE also skips the check_tsc_warp() tests in
tsc_sync.c.
This means that if someone does a Goldmont BIOS with 'features', we'll
never detect the wreckage :-/
next prev parent reply other threads:[~2016-10-20 10:17 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-16 17:42 [PATCH v2] x86/tsc: Set X86_FEATURE_TSC_RELIABLE to skip refined calibration Bin Gao
2016-08-24 8:51 ` Thomas Gleixner
2016-08-25 16:43 ` Bin Gao
2016-08-26 10:11 ` Thomas Gleixner
2016-08-26 10:14 ` Thomas Gleixner
2016-10-11 21:11 ` Bin Gao
2016-10-12 7:52 ` Thomas Gleixner
2016-10-13 23:16 ` [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Bin Gao
2016-10-20 9:57 ` Thomas Gleixner
2016-10-20 10:17 ` Peter Zijlstra [this message]
2016-10-20 19:37 ` Thomas Gleixner
2016-10-21 5:47 ` Peter Zijlstra
2016-10-21 8:05 ` Thomas Gleixner
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