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From: Thomas Gleixner <tglx@linutronix.de>
To: Peter Zijlstra <peterz@infradead.org>
Cc: Bin Gao <bin.gao@linux.intel.com>, Ingo Molnar <mingo@redhat.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	John Stultz <john.stultz@linaro.org>,
	x86@kernel.org, linux-kernel@vger.kernel.org, bin.gao@intel.com
Subject: Re: [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag
Date: Fri, 21 Oct 2016 10:05:42 +0200 (CEST)	[thread overview]
Message-ID: <alpine.DEB.2.20.1610211005130.4797@nanos> (raw)
In-Reply-To: <20161021054717.GZ3102@twins.programming.kicks-ass.net>

On Fri, 21 Oct 2016, Peter Zijlstra wrote:
> On Thu, Oct 20, 2016 at 09:37:50PM +0200, Thomas Gleixner wrote:
> 
> > Well, we have the same issue on other platforms/models which set the
> > reliable flag.
> 
> I was not aware we had other platforms doing this, git grep tells me
> intel-mid does this as well..
> 
> > So one sanity check we can do is to read the IA32_TSC_ADJUST MSR on all
> > cores. They should all have the same value (usually 0) or at least have a
> > very minimal delta. If that's off by more than 1us then something is fishy
> > especially on single socket systems. We could at least WARN about it.
> > 
> > We could do this in idle occasionally as well, so we can detect the dreaded
> > "SMI wants to hide the cycles" crapola.
> 
> Indeed, that sounds like the best we can; and probably should; do.

I'll have a look at that in the next days.

Thanks,

	tglx
 

      reply	other threads:[~2016-10-21  8:08 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-16 17:42 [PATCH v2] x86/tsc: Set X86_FEATURE_TSC_RELIABLE to skip refined calibration Bin Gao
2016-08-24  8:51 ` Thomas Gleixner
2016-08-25 16:43   ` Bin Gao
2016-08-26 10:11     ` Thomas Gleixner
2016-08-26 10:14       ` Thomas Gleixner
2016-10-11 21:11         ` Bin Gao
2016-10-12  7:52           ` Thomas Gleixner
2016-10-13 23:16             ` [PATCH v3] x86/tsc: add X86_FEATURE_TSC_KNOWN_FREQ flag Bin Gao
2016-10-20  9:57               ` Thomas Gleixner
2016-10-20 10:17                 ` Peter Zijlstra
2016-10-20 19:37                   ` Thomas Gleixner
2016-10-21  5:47                     ` Peter Zijlstra
2016-10-21  8:05                       ` Thomas Gleixner [this message]

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