From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Lee Jones <lee.jones@linaro.org>, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1 1/1] mfd: intel-lpss: Try to enable Memory-Write-Invalidate
Date: Thu, 10 Nov 2016 18:39:39 +0200 [thread overview]
Message-ID: <20161110163939.GN1470@lahna.fi.intel.com> (raw)
In-Reply-To: <1478791360.5295.119.camel@linux.intel.com>
On Thu, Nov 10, 2016 at 05:22:40PM +0200, Andy Shevchenko wrote:
> On Thu, 2016-11-10 at 16:59 +0200, Mika Westerberg wrote:
> > On Thu, Nov 10, 2016 at 04:51:42PM +0200, Andy Shevchenko wrote:
> > > Enable MWI mechanism if PCI bus master supports it.
> >
> > Why?
>
> It might be potential benefit in some cases. Documentation says that
> standard Memory Write might supply more current data than in the CPU
> modified cache line and "trashing a line in the cache may trash some
> data that is more current that in the memory line". This allows to avoid
> potential retries and other performance degradation issues on the bus.
> Though, I dunno how to measure it.
>
> Would be enough to extend commit message by this paragraph?
That's better, yes.
prev parent reply other threads:[~2016-11-10 16:44 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-10 14:51 Andy Shevchenko
2016-11-10 14:59 ` Mika Westerberg
2016-11-10 15:22 ` Andy Shevchenko
2016-11-10 16:39 ` Mika Westerberg [this message]
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