From: Maxime Ripard <maxime.ripard@free-electrons.com>
To: Icenowy Zheng <icenowy@aosc.xyz>
Cc: Jaroslav Kysela <perex@perex.cz>,
Vinod Koul <vinod.koul@intel.com>,
linux-gpio@vger.kernel.org, dmaengine@vger.kernel.org,
Chen-Yu Tsai <wens@csie.org>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
Andre Przywara <andre.przywara@arm.com>,
devicetree@vger.kernel.org, Mark Brown <broonie@kernel.org>,
alsa-devel@alsa-project.org,
Linus Walleij <linus.walleij@linaro.org>,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@googlegroups.com
Subject: Re: [linux-sunxi] Re: [PATCH v3 04/10] clk: sunxi-ng: add support for Allwinner H5 SoC
Date: Tue, 7 Feb 2017 16:56:05 +0100 [thread overview]
Message-ID: <20170207155605.f2k44gr56ywehz3t@lukather> (raw)
In-Reply-To: <20170207000838.8UJeKISe@smtp2p.mail.yandex.net>
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On Mon, Jan 30, 2017 at 10:02:04PM +0800, Icenowy Zheng wrote:
> > > static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
> > > [RST_USB_PHY0] = { 0x0cc, BIT(0) },
> > > [RST_USB_PHY1] = { 0x0cc, BIT(1) },
> > > @@ -791,6 +910,7 @@ static struct ccu_reset_map sunxi_h3_h5_ccu_resets[] = {
> > > [RST_BUS_UART2] = { 0x2d8, BIT(18) },
> > > [RST_BUS_UART3] = { 0x2d8, BIT(19) },
> > > [RST_BUS_SCR0] = { 0x2d8, BIT(20) },
> > > + [RST_BUS_SCR1] = { 0x2d8, BIT(21) },
> >
> > That reset line is not valid on the H3.
>
> So I should split a H3 reset array and a H5 one?
Ideally, yes.
> (I modelled after ccu-sun5i.c, which shares one reset array)
They all share the same reset lines.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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parent reply other threads:[~2017-02-07 15:56 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <20170207000838.8UJeKISe@smtp2p.mail.yandex.net>]
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