From: Kyle Huey <me@kylehuey.com>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andy Lutomirski <luto@kernel.org>,
x86@kernel.org
Subject: [PATCH v2 2/3] x86/process: Correct and optimize TIF_BLOCKSTEP switch
Date: Tue, 14 Feb 2017 00:11:03 -0800 [thread overview]
Message-ID: <20170214081104.9244-3-khuey@kylehuey.com> (raw)
In-Reply-To: <20170214081104.9244-1-khuey@kylehuey.com>
Because the MSR is "highly magical", reset DEBUGCTLMSR_BTF on every task
switch in or out of a task that uses TIF_BLOCKSTEP, even if both tasks
have TIF_BLOCKSTEP set. Avoid branching within the TIF_BLOCKSTEP case
and evaluating boot_cpu_data twice in kernels without
CONFIG_X86_DEBUGCTLMSR.
x86_64: arch/x86/kernel/process.o
text data bss dec hex
3024 8577 16 11617 2d61 Before
3008 8577 16 11601 2d51 After
i386: No change
Originally-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Kyle Huey <khuey@kylehuey.com>
---
arch/x86/include/asm/msr-index.h | 1 +
arch/x86/kernel/process.c | 12 ++++++------
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 710273c617b8..a8997a7b4e74 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -127,6 +127,7 @@
/* DEBUGCTLMSR bits (others vary by model): */
#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */
+#define _DEBUGCTLMSR_BTF 1
#define DEBUGCTLMSR_BTF (1UL << 1) /* single-step on branches */
#define DEBUGCTLMSR_TR (1UL << 6)
#define DEBUGCTLMSR_BTS (1UL << 7)
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 01ef6f63d5fb..5dd08328108e 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -209,13 +209,13 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
propagate_user_return_notify(prev_p, next_p);
- if ((tifp ^ tifn) & _TIF_BLOCKSTEP) {
- unsigned long debugctl = get_debugctlmsr();
-
+ if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
+ arch_has_block_step()) {
+ unsigned long debugctl;
+ rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
debugctl &= ~DEBUGCTLMSR_BTF;
- if (tifn & _TIF_BLOCKSTEP)
- debugctl |= DEBUGCTLMSR_BTF;
- update_debugctlmsr(debugctl);
+ debugctl |= (tifn & _TIF_BLOCKSTEP) >> TIF_BLOCKSTEP << _DEBUGCTLMSR_BTF;
+ wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
}
if ((tifp ^ tifn) & _TIF_NOTSC) {
--
2.11.0
next prev parent reply other threads:[~2017-02-14 8:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-14 8:11 [PATCH v2 0/3] x86/process: Optimize __switch_to_xtra() Kyle Huey
2017-02-14 8:11 ` [PATCH v2 1/3] x86/process: Optimize TIF checks in __switch_to_xtra() Kyle Huey
2017-03-11 11:49 ` [tip:x86/process] " tip-bot for Kyle Huey
2017-02-14 8:11 ` Kyle Huey [this message]
2017-03-11 11:49 ` [tip:x86/process] x86/process: Correct and optimize TIF_BLOCKSTEP switch tip-bot for Kyle Huey
2017-02-14 8:11 ` [PATCH v2 3/3] x86/process: Optimize TIF_NOTSC switch Kyle Huey
2017-03-11 11:50 ` [tip:x86/process] " tip-bot for Thomas Gleixner
2017-02-28 18:33 ` [PATCH v2 0/3] x86/process: Optimize __switch_to_xtra() Kyle Huey
2017-03-08 22:07 ` Kyle Huey
2017-03-10 20:23 ` Thomas Gleixner
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