From: Kyle Huey <me@kylehuey.com>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andy Lutomirski <luto@kernel.org>,
x86@kernel.org
Subject: [PATCH v2 3/3] x86/process: Optimize TIF_NOTSC switch
Date: Tue, 14 Feb 2017 00:11:04 -0800 [thread overview]
Message-ID: <20170214081104.9244-4-khuey@kylehuey.com> (raw)
In-Reply-To: <20170214081104.9244-1-khuey@kylehuey.com>
From: Thomas Gleixner <tglx@linutronix.de>
Provide and use a toggle helper instead of doing it with a branch.
x86_64: arch/x86/kernel/process.o
text data bss dec hex
3008 8577 16 11601 2d51 Before
2976 8577 16 11569 2d31 After
i386: arch/x86/kernel/process.o
text data bss dec hex
2925 8673 8 11606 2d56 Before
2893 8673 8 11574 2d36 After
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/include/asm/tlbflush.h | 10 ++++++++++
arch/x86/kernel/process.c | 22 ++++------------------
2 files changed, 14 insertions(+), 18 deletions(-)
diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
index 6fa85944af83..ff4923a19f79 100644
--- a/arch/x86/include/asm/tlbflush.h
+++ b/arch/x86/include/asm/tlbflush.h
@@ -110,6 +110,16 @@ static inline void cr4_clear_bits(unsigned long mask)
}
}
+static inline void cr4_toggle_bits(unsigned long mask)
+{
+ unsigned long cr4;
+
+ cr4 = this_cpu_read(cpu_tlbstate.cr4);
+ cr4 ^= mask;
+ this_cpu_write(cpu_tlbstate.cr4, cr4);
+ __write_cr4(cr4);
+}
+
/* Read the CR4 shadow. */
static inline unsigned long cr4_read_shadow(void)
{
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 5dd08328108e..ebf2c06839bd 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -116,11 +116,6 @@ void flush_thread(void)
fpu__clear(&tsk->thread.fpu);
}
-static void hard_disable_TSC(void)
-{
- cr4_set_bits(X86_CR4_TSD);
-}
-
void disable_TSC(void)
{
preempt_disable();
@@ -129,15 +124,10 @@ void disable_TSC(void)
* Must flip the CPU state synchronously with
* TIF_NOTSC in the current running context.
*/
- hard_disable_TSC();
+ cr4_set_bits(X86_CR4_TSD);
preempt_enable();
}
-static void hard_enable_TSC(void)
-{
- cr4_clear_bits(X86_CR4_TSD);
-}
-
static void enable_TSC(void)
{
preempt_disable();
@@ -146,7 +136,7 @@ static void enable_TSC(void)
* Must flip the CPU state synchronously with
* TIF_NOTSC in the current running context.
*/
- hard_enable_TSC();
+ cr4_clear_bits(X86_CR4_TSD);
preempt_enable();
}
@@ -218,12 +208,8 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
}
- if ((tifp ^ tifn) & _TIF_NOTSC) {
- if (tifn & _TIF_NOTSC)
- hard_disable_TSC();
- else
- hard_enable_TSC();
- }
+ if ((tifp ^ tifn) & _TIF_NOTSC)
+ cr4_toggle_bits(X86_CR4_TSD);
}
/*
--
2.11.0
next prev parent reply other threads:[~2017-02-14 8:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-14 8:11 [PATCH v2 0/3] x86/process: Optimize __switch_to_xtra() Kyle Huey
2017-02-14 8:11 ` [PATCH v2 1/3] x86/process: Optimize TIF checks in __switch_to_xtra() Kyle Huey
2017-03-11 11:49 ` [tip:x86/process] " tip-bot for Kyle Huey
2017-02-14 8:11 ` [PATCH v2 2/3] x86/process: Correct and optimize TIF_BLOCKSTEP switch Kyle Huey
2017-03-11 11:49 ` [tip:x86/process] " tip-bot for Kyle Huey
2017-02-14 8:11 ` Kyle Huey [this message]
2017-03-11 11:50 ` [tip:x86/process] x86/process: Optimize TIF_NOTSC switch tip-bot for Thomas Gleixner
2017-02-28 18:33 ` [PATCH v2 0/3] x86/process: Optimize __switch_to_xtra() Kyle Huey
2017-03-08 22:07 ` Kyle Huey
2017-03-10 20:23 ` Thomas Gleixner
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