From: Kishon Vijay Abraham I <kishon@ti.com>
To: <gregkh@linuxfoundation.org>
Cc: <kishon@ti.com>, <linux-kernel@vger.kernel.org>
Subject: [PATCH 11/32] phy: exynos-mipi-video: Use consistent method to address phy registers
Date: Mon, 10 Apr 2017 18:48:02 +0530 [thread overview]
Message-ID: <20170410131823.26485-12-kishon@ti.com> (raw)
In-Reply-To: <20170410131823.26485-1-kishon@ti.com>
From: Krzysztof Kozlowski <krzk@kernel.org>
Exynos4 MIPI phy registers are defined with macro calculating the offset
for given phyN. Use the same method for Exynos5420 to be consistent.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/phy-exynos-mipi-video.c | 20 ++++++++++----------
include/linux/soc/samsung/exynos-regs-pmu.h | 4 +---
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/phy/phy-exynos-mipi-video.c b/drivers/phy/phy-exynos-mipi-video.c
index d7fe1f8c3ac8..acef1d92691e 100644
--- a/drivers/phy/phy-exynos-mipi-video.c
+++ b/drivers/phy/phy-exynos-mipi-video.c
@@ -110,46 +110,46 @@ static const struct mipi_phy_device_desc exynos5420_mipi_phy = {
/* EXYNOS_MIPI_PHY_ID_CSIS0 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM0,
.enable_val = EXYNOS5_PHY_ENABLE,
- .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+ .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
- .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+ .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
}, {
/* EXYNOS_MIPI_PHY_ID_DSIM0 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS0,
.enable_val = EXYNOS5_PHY_ENABLE,
- .enable_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+ .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
- .resetn_reg = EXYNOS5420_MIPI_PHY0_CONTROL,
+ .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(0),
.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
}, {
/* EXYNOS_MIPI_PHY_ID_CSIS1 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_DSIM1,
.enable_val = EXYNOS5_PHY_ENABLE,
- .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+ .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
- .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+ .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
}, {
/* EXYNOS_MIPI_PHY_ID_DSIM1 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_CSIS1,
.enable_val = EXYNOS5_PHY_ENABLE,
- .enable_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+ .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = EXYNOS5_MIPI_PHY_M_RESETN,
- .resetn_reg = EXYNOS5420_MIPI_PHY1_CONTROL,
+ .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(1),
.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
}, {
/* EXYNOS_MIPI_PHY_ID_CSIS2 */
.coupled_phy_id = EXYNOS_MIPI_PHY_ID_NONE,
.enable_val = EXYNOS5_PHY_ENABLE,
- .enable_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
+ .enable_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
.enable_map = EXYNOS_MIPI_REGMAP_PMU,
.resetn_val = EXYNOS5_MIPI_PHY_S_RESETN,
- .resetn_reg = EXYNOS5420_MIPI_PHY2_CONTROL,
+ .resetn_reg = EXYNOS5420_MIPI_PHY_CONTROL(2),
.resetn_map = EXYNOS_MIPI_REGMAP_PMU,
},
},
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index 4ee54b3fcd57..c261ed927e1e 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -505,9 +505,7 @@
((EXYNOS5420_KFC_CORE_RESET0 | EXYNOS5420_KFC_ETM_RESET0) << (_nr))
#define EXYNOS5420_USBDRD1_PHY_CONTROL 0x0708
-#define EXYNOS5420_MIPI_PHY0_CONTROL 0x0714
-#define EXYNOS5420_MIPI_PHY1_CONTROL 0x0718
-#define EXYNOS5420_MIPI_PHY2_CONTROL 0x071C
+#define EXYNOS5420_MIPI_PHY_CONTROL(n) (0x0714 + (n) * 4)
#define EXYNOS5420_DPTX_PHY_CONTROL 0x0728
#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG 0x1020
#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG 0x1024
--
2.11.0
next prev parent reply other threads:[~2017-04-10 13:18 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-10 13:17 [GIT PULL] phy: for 4.12 Kishon Vijay Abraham I
2017-04-10 13:17 ` [PATCH 01/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Kishon Vijay Abraham I
2017-04-11 14:14 ` Lee Jones
2017-04-11 14:20 ` Greg KH
2017-04-11 14:24 ` Kishon Vijay Abraham I
2017-04-11 16:34 ` Lee Jones
2017-04-12 5:19 ` Kishon Vijay Abraham I
2017-04-12 7:57 ` Lee Jones
2017-04-10 13:17 ` [PATCH 02/32] phy: phy-exynos-pcie: make it explicitly non-modular Kishon Vijay Abraham I
2017-04-10 13:17 ` [PATCH 03/32] mfd: exynos-lpass: Use common soc/exynos-regs-pmu.h header Kishon Vijay Abraham I
2017-04-10 13:17 ` [PATCH 04/32] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Kishon Vijay Abraham I
2017-04-10 13:17 ` [PATCH 05/32] phy: sun4i-usb: change PHYCTL register clearing code Kishon Vijay Abraham I
2017-04-10 13:17 ` [PATCH 06/32] phy: sun4i-usb: add PHYCTL offset for H3 SoC Kishon Vijay Abraham I
2017-04-10 13:17 ` [PATCH 07/32] phy: sun4i-usb: support automatically switch PHY0 route to MUSB/HCI Kishon Vijay Abraham I
2017-04-10 13:17 ` [PATCH 08/32] phy: meson8b-usb2: fix offsets for some of the registers Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 09/32] phy: exynos4: Remove duplicated defines of PHY register defines Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 10/32] phy: exynos5: " Kishon Vijay Abraham I
2017-04-10 13:18 ` Kishon Vijay Abraham I [this message]
2017-04-10 13:18 ` [PATCH 12/32] phy: exynos: Use one define for enable bit Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 13/32] phy: rockchip-inno-usb2: fix spelling mistake: "connecetd" -> "connected" Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 14/32] phy: rcar-gen3-usb2: fix implementation for runtime PM Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 15/32] phy: sun4i-usb: enable PHY0 dual route switching for A64 USB PHY Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 16/32] phy: phy-mt65xx-usb3: improve RX detection stable time Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 17/32] phy: phy-mt65xx-usb3: increase LFPS filter threshold Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 18/32] phy: phy-mt65xx-usb3: split SuperSpeed port into two ones Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 19/32] phy: phy-mt65xx-usb3: move clock from phy node into port nodes Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 20/32] phy: phy-mt65xx-usb3: add support for new version phy Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 21/32] phy: phy-mt65xx-usb3: disable 100uA extraction from SS port to HS port Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 22/32] dt-bindings: phy-mt65xx-usb: add support for new version phy Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 23/32] dt-bindings: phy-rockchip-inno-usb2: add assign clock property in usb2-phy node Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 24/32] dt-bindings: add DT bindings for usb2-phy grf Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 25/32] phy: rockchip-inno-usb2: add support of usb2-phy for rk3328 Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 26/32] dt-bindings: phy: Add support for QUSB2 phy Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 27/32] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 28/32] dt-bindings: phy: Add support for QMP phy Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 29/32] phy: qcom-qmp: new qmp phy driver for qcom-chipsets Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 30/32] phy: bcm-ns-usb3: split all writes into reg & val pairs Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 31/32] phy: rockchip-usb: Add vbus regulator support Kishon Vijay Abraham I
2017-04-10 13:18 ` [PATCH 32/32] phy: qcom-qusb2: add NVMEM dependency Kishon Vijay Abraham I
2017-04-10 13:46 ` [GIT PULL] phy: for 4.12 Greg KH
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