[PATCH] kdump test comments:

[PATCH] kdump test comments:

[yanjiang.jin]

From: Yanjiang Jin <yanjiang.jin@windriver.com>

1. Execute a kdump test on a "Freescale LayerScape LS1021E, Version: 2.0 board";

2. I think may all "proc-v7-3level" CPUs need this patch, but I only validated it on LS1021, so still use

#ifdef CONFIG_SOC_LS1021A

   to wrap this change;

3. Append "crashkernel=128M@2560M" in UBoot's command line;

4. Use uImage as kdump's first kernel and capture kernel, but ls1021A doesn't define LOADADDR now,
   so add below code in "arch/arm/boot/Makefile" temporarily to build an uImage:

+ifeq ($(CONFIG_SOC_LS1021A), y)
+LOADADDR=0x80008000
+endif
+

Yanjiang Jin (1):
  arm: proc-v7-3level.S: SOC_LS1021A: clear TTBCR.T1SZ

 arch/arm/mm/proc-v7-3level.S | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

-- 
1.9.1

[PATCH] arm: proc-v7-3level.S: SOC_LS1021A: clear TTBCR.T1SZ

[yanjiang.jin]

From: Yanjiang Jin <yanjiang.jin@windriver.com>

The macro "v7_ttb_setup" will set "TTBCR.T1SZ" only when
"PHYS_OFFSET <= PAGE_OFFSET".
But if we load the second kernel during kdump boot, PHYS_OFFSET may be
greater than PAGE_OFFSET, we don't want to set this bit, but TTBCR.T1SZ
is still not zero since the first kernel's value is reserved.
In this circumstance, the second kernel would hang once the MMU is enabled.

Signed-off-by: Yanjiang Jin <yanjiang.jin@windriver.com>
---
 arch/arm/mm/proc-v7-3level.S | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 5e5720e..b6ca5eb 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -140,12 +140,16 @@ ENDPROC(cpu_v7_set_pte_ext)
 	 * otherwise booting secondary CPUs would end up using TTBR1 for the
 	 * identity mapping set up in TTBR0.
 	 */
-	orrls	\tmp, \tmp, #TTBR1_SIZE				@ TTBCR.T1SZ
-	mcr	p15, 0, \tmp, c2, c0, 2				@ TTBCR
+
+#ifdef CONFIG_SOC_LS1021A
+	bic	\tmp, \tmp, #TTBR1_SIZE		@ clear TTBCR.T1SZ first
+#endif
+	orrls	\tmp, \tmp, #TTBR1_SIZE		@ TTBCR.T1SZ
+	mcr	p15, 0, \tmp, c2, c0, 2		@ TTBCR
 	mov	\tmp, \ttbr1, lsr #20
 	mov	\ttbr1, \ttbr1, lsl #12
 	addls	\ttbr1, \ttbr1, #TTBR1_OFFSET
-	mcrr	p15, 1, \ttbr1, \tmp, c2			@ load TTBR1
+	mcrr	p15, 1, \ttbr1, \tmp, c2	@ load TTBR1
 	.endm
 
 	/*
-- 
1.9.1