From: Peter Zijlstra <peterz@infradead.org>
To: tglx@linutronix.de
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
kevin.b.stanton@intel.com, peterz@infradead.org
Subject: [PATCH 3/3] x86/tsc: Remove the TSC_ADJUST clamp
Date: Wed, 31 May 2017 17:52:04 +0200 [thread overview]
Message-ID: <20170531155306.100950003@infradead.org> (raw)
In-Reply-To: <20170531155201.218077283@infradead.org>
[-- Attachment #1: peterz-tscadj-normalize.patch --]
[-- Type: text/plain, Size: 2047 bytes --]
Now that all affected platforms have a microcode update; and we check
this and disable TSC_DEADLINE and print a microcode revision update
error if its too old, we can remove the TSC_ADJUST clamp.
This should help with systems where the second socket runs ahead of
the first socket and needs a negative adjustment. In this case we'd
hit the 0 clamp and give up for not achieving synchronization.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
arch/x86/kernel/tsc_sync.c | 21 +--------------------
1 file changed, 1 insertion(+), 20 deletions(-)
--- a/arch/x86/kernel/tsc_sync.c
+++ b/arch/x86/kernel/tsc_sync.c
@@ -71,13 +71,8 @@ static void tsc_sanitize_first_cpu(struc
* non zero. We don't do that on non boot cpus because physical
* hotplug should have set the ADJUST register to a value > 0 so
* the TSC is in sync with the already running cpus.
- *
- * But we always force positive ADJUST values. Otherwise the TSC
- * deadline timer creates an interrupt storm. We also have to
- * prevent values > 0x7FFFFFFF as those wreckage the timer as well.
*/
- if ((bootcpu && bootval != 0) || (!bootcpu && bootval < 0) ||
- (bootval > 0x7FFFFFFF)) {
+ if (bootcpu && bootval != 0) {
pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", cpu,
bootval);
wrmsrl(MSR_IA32_TSC_ADJUST, 0);
@@ -451,20 +446,6 @@ void check_tsc_sync_target(void)
*/
cur->adjusted += cur_max_warp;
- /*
- * TSC deadline timer stops working or creates an interrupt storm
- * with adjust values < 0 and > x07ffffff.
- *
- * To allow adjust values > 0x7FFFFFFF we need to disable the
- * deadline timer and use the local APIC timer, but that requires
- * more intrusive changes and we do not have any useful information
- * from Intel about the underlying HW wreckage yet.
- */
- if (cur->adjusted < 0)
- cur->adjusted = 0;
- if (cur->adjusted > 0x7FFFFFFF)
- cur->adjusted = 0x7FFFFFFF;
-
pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n",
cpu, cur_max_warp, cur->adjusted);
next prev parent reply other threads:[~2017-05-31 15:56 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-31 15:52 [PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode revisions Peter Zijlstra
2017-05-31 15:52 ` [PATCH 1/3] x86/apic: Change the lapic name in deadline mode Peter Zijlstra
2017-06-04 20:01 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
2017-05-31 15:52 ` [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Peter Zijlstra
2017-05-31 21:58 ` Henrique de Moraes Holschuh
2017-06-01 9:35 ` Peter Zijlstra
2017-06-01 9:58 ` Thomas Gleixner
2017-06-01 17:29 ` Henrique de Moraes Holschuh
2017-06-04 20:01 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
2017-05-31 15:52 ` Peter Zijlstra [this message]
2017-06-04 20:02 ` [tip:x86/timers] x86/tsc: Remove the TSC_ADJUST clamp tip-bot for Peter Zijlstra
2017-05-31 18:38 ` [PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode revisions Henrique de Moraes Holschuh
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