From: Henrique de Moraes Holschuh <hmh@hmh.eng.br>
To: Peter Zijlstra <peterz@infradead.org>
Cc: tglx@linutronix.de, x86@kernel.org, linux-kernel@vger.kernel.org,
kevin.b.stanton@intel.com
Subject: Re: [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata
Date: Wed, 31 May 2017 18:58:55 -0300 [thread overview]
Message-ID: <20170531215855.GA5382@khazad-dum.debian.net> (raw)
In-Reply-To: <20170531155306.050849877@infradead.org>
On Wed, 31 May 2017, Peter Zijlstra wrote:
> + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014),
...
> + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2),
> + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2),
...
> + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52),
> + DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52),
Maybe these revisions need to be decreased by one, so that the SGX
behavior of messing with the microcode revision is taken into account?
When the processor microcode is auto-updated from the (signed) FIT, and
SGX's PRMRR feature is supported, the processor will report its
microcode revision as one less. Therefore, a microcode update with
revision 0xb2 auto-loaded from FIT would be reported by RDMSR(0x8b) as
revision 0xb1.
I know about this SGX-related behavior from a coreboot commit from ~two
years ago (link below). As far as I can tell, the Intel 64/IA32 SDM is
*still* missing any mention about this behavior in vol 3A section 9.11
(where it describes microcode updates).
https://review.coreboot.org/cgit/coreboot.git/commit/?id=5042aad4ded1651638ae9b60e34114b65e4f211e
--
Henrique Holschuh
next prev parent reply other threads:[~2017-05-31 21:59 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-05-31 15:52 [PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode revisions Peter Zijlstra
2017-05-31 15:52 ` [PATCH 1/3] x86/apic: Change the lapic name in deadline mode Peter Zijlstra
2017-06-04 20:01 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
2017-05-31 15:52 ` [PATCH 2/3] x86/apic: Add TSC_DEADLINE quirk due to errata Peter Zijlstra
2017-05-31 21:58 ` Henrique de Moraes Holschuh [this message]
2017-06-01 9:35 ` Peter Zijlstra
2017-06-01 9:58 ` Thomas Gleixner
2017-06-01 17:29 ` Henrique de Moraes Holschuh
2017-06-04 20:01 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
2017-05-31 15:52 ` [PATCH 3/3] x86/tsc: Remove the TSC_ADJUST clamp Peter Zijlstra
2017-06-04 20:02 ` [tip:x86/timers] " tip-bot for Peter Zijlstra
2017-05-31 18:38 ` [PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode revisions Henrique de Moraes Holschuh
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