From: Boqun Feng <boqun.feng@gmail.com>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Olof Johansson <olof@lixom.net>, Arnd Bergmann <arnd@arndb.de>,
akpm@linux-foundation.org, albert@sifive.com,
yamada.masahiro@socionext.com, mmarek@suse.com,
will.deacon@arm.com, peterz@infradead.org, mingo@redhat.com,
daniel.lezcano@linaro.org, tglx@linutronix.de,
jason@lakedaemon.net, marc.zyngier@arm.com,
gregkh@linuxfoundation.org, jslaby@suse.com, davem@davemloft.net,
mchehab@kernel.org, sfr@canb.auug.org.au, fweisbec@gmail.com,
viro@zeniv.linux.org.uk, mcgrof@kernel.org, dledford@redhat.com,
bart.vanassche@sandisk.com, sstabellini@kernel.org,
daniel.vetter@ffwll.ch, mpe@ellerman.id.au, msalter@redhat.com,
nicolas.dichtel@6wind.com, james.hogan@imgtec.com,
paul.gortmaker@windriver.com, linux@roeck-us.net,
heiko.carstens@de.ibm.com, schwidefsky@de.ibm.com,
linux-kernel@vger.kernel.org, patches@groups.riscv.org
Subject: Re: [PATCH 10/17] RISC-V: Atomic and Locking Code
Date: Wed, 12 Jul 2017 20:44:06 +0800 [thread overview]
Message-ID: <20170712124406.jectd7nj4wfx5ign@tardis> (raw)
In-Reply-To: <20170712124049.i7taml22aat2bcgt@tardis>
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On Wed, Jul 12, 2017 at 08:40:49PM +0800, Boqun Feng wrote:
[...]
> > +/**
> > + * set_bit - Atomically set a bit in memory
> > + * @nr: the bit to set
> > + * @addr: the address to start counting from
> > + *
> > + * This function is atomic and may not be reordered. See __set_bit()
>
> This is incorrect, {set,change,clear}_bit() can be reordered, see
> Documentation/memory-barriers.txt, they are just relaxed atomics. But I
> think you just copy this from x86 code, so maybe x86 code needs help
> too, at least claim that's only x86-specific guarantee.
>
> > + * if you do not require the atomic guarantees.
> > + *
> > + * Note: there are no guarantees that this function will not be reordered
> > + * on non x86 architectures, so if you are writing portable code,
> > + * make sure not to rely on its reordering guarantees.
> > + *
Hmmm.. the claim is right here ;-/
As your implementation is relax semantics, you'd better rewrite the
comment ;-)
Regards,
Boqun
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next prev parent reply other threads:[~2017-07-12 12:44 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-12 1:31 RISC-V Linux Port v6 Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 01/17] lib: Add shared copies of some GCC library routines Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 02/17] pci: Add a generic, weakly-linked pcibios_align_resource Palmer Dabbelt
2017-07-12 13:41 ` Luis R. Rodriguez
2017-07-12 22:50 ` Bjorn Helgaas
2017-07-13 18:30 ` Palmer Dabbelt
2017-07-14 3:19 ` kbuild test robot
2017-07-12 1:31 ` [PATCH 03/17] pci: Add a generic, weakly-linked pcibios_fixup_bus Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 04/17] MAINTAINERS: Add RISC-V Palmer Dabbelt
2017-07-12 11:16 ` James Hogan
2017-07-12 11:31 ` Arnd Bergmann
2017-07-12 14:51 ` [patches] " Jonathan Neuschäfer
2017-07-12 1:31 ` [PATCH 05/17] clocksource: New RISC-V SBI timer driver Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 06/17] irqchip: RISC-V Local Interrupt Controller Driver Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 07/17] irqchip: New RISC-V PLIC Driver Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 08/17] tty: New RISC-V SBI console driver Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 09/17] RISC-V: Init and Halt Code Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 10/17] RISC-V: Atomic and Locking Code Palmer Dabbelt
2017-07-12 12:40 ` Boqun Feng
2017-07-12 12:44 ` Boqun Feng [this message]
2017-07-12 12:49 ` Peter Zijlstra
2017-07-12 17:17 ` Palmer Dabbelt
2017-07-12 13:13 ` Arnd Bergmann
2017-07-12 1:31 ` [PATCH 11/17] RISC-V: Generic library routines and assembly Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 12/17] RISC-V: ELF and module implementation Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 13/17] RISC-V: Task implementation Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 14/17] RISC-V: Device, timer, IRQs, and the SBI Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 15/17] RISC-V: Paging and MMU Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 16/17] RISC-V: User-facing API Palmer Dabbelt
2017-07-12 11:07 ` James Hogan
2017-07-12 16:24 ` Palmer Dabbelt
2017-07-12 17:09 ` James Hogan
2017-07-13 21:50 ` Palmer Dabbelt
2017-07-12 1:31 ` [PATCH 17/17] RISC-V: Build Infastructure Palmer Dabbelt
2017-07-26 2:57 ` [patches] " Jonathan Neuschäfer
2017-07-26 5:20 ` Palmer Dabbelt
2017-07-26 6:52 ` Arnd Bergmann
2017-07-26 18:37 ` Jonathan Neuschäfer
2017-07-12 7:58 ` RISC-V Linux Port v6 Arnd Bergmann
2017-07-12 13:53 ` Luis R. Rodriguez
2017-07-12 17:55 ` Will Deacon
2017-07-12 19:34 ` Arnd Bergmann
-- strict thread matches above, loose matches on Subject: below --
2017-07-11 1:39 RISC-V Linux Port v5 Palmer Dabbelt
2017-07-11 1:39 ` [PATCH 10/17] RISC-V: Atomic and Locking Code Palmer Dabbelt
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