From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Bin Meng <bmeng.cn@gmail.com>
Cc: Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
Marek Vasut <marek.vasut@gmail.com>,
Boris Brezillon <boris.brezillon@free-electrons.com>,
Brian Norris <computersforpeace@gmail.com>,
Richard Weinberger <richard@nod.at>,
David Woodhouse <dwmw2@infradead.org>,
linux-mtd <linux-mtd@lists.infradead.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Stefan Roese <sr@denx.de>
Subject: Re: [PATCH 10/10] spi-nor: intel-spi: Fall back to use SW sequencer to erase
Date: Fri, 1 Sep 2017 12:52:47 +0300 [thread overview]
Message-ID: <20170901095247.GY2598@lahna.fi.intel.com> (raw)
In-Reply-To: <1504252841-2445-11-git-send-email-bmeng.cn@gmail.com>
On Fri, Sep 01, 2017 at 01:00:41AM -0700, Bin Meng wrote:
> /*
> + * Determine whether erase operatoin should use HW or SW sequencer.
^^^^^^^^^
Typo
> + *
> + * The HW sequencer has a predefined list of opcodes, with only the
> + * erase opcode being programmable in LVSCC and UVSCC registers.
> + * If these registers don't contain a valid erase opcode, erase
> + * cannot be done using HW sequencer.
> + */
next prev parent reply other threads:[~2017-09-01 9:59 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-01 8:00 [PATCH 00/10] spi-nor: intel-spi: Various fixes and enhancements Bin Meng
2017-09-01 8:00 ` [PATCH 01/10] spi-nor: intel-spi: Fix number of protected range registers for BYT/LPT Bin Meng
2017-09-01 9:52 ` Marek Vasut
2017-09-11 2:46 ` Bin Meng
2017-09-01 8:00 ` [PATCH 02/10] spi-nor: intel-spi: Remove useless 'buf' parameter in the HW/SW cycle Bin Meng
2017-09-01 8:00 ` [PATCH 03/10] spi-nor: intel-spi: Fix broken software sequencing codes Bin Meng
2017-09-01 9:45 ` Mika Westerberg
2017-09-01 8:00 ` [PATCH 04/10] spi-nor: intel-spi: Check transfer length in the HW/SW cycle Bin Meng
2017-09-01 8:00 ` [PATCH 05/10] spi-nor: intel-spi: Use SW sequencer for BYT/LPT Bin Meng
2017-09-01 8:00 ` [PATCH 06/10] spi-nor: intel-spi: Remove 'Atomic Cycle Sequence' in intel_spi_write() Bin Meng
2017-09-01 8:00 ` [PATCH 07/10] spi-nor: intel-spi: Don't assume OPMENU0/1 to be programmed by BIOS Bin Meng
2017-09-01 8:00 ` [PATCH 08/10] spi-nor: intel-spi: Remove the unnecessary HSFSTS register RW Bin Meng
2017-09-01 8:00 ` [PATCH 09/10] spi-nor: intel-spi: Rename swseq to swseq_reg in 'struct intel_spi' Bin Meng
2017-09-01 8:00 ` [PATCH 10/10] spi-nor: intel-spi: Fall back to use SW sequencer to erase Bin Meng
2017-09-01 9:52 ` Mika Westerberg [this message]
2017-09-01 10:09 ` [PATCH 00/10] spi-nor: intel-spi: Various fixes and enhancements Mika Westerberg
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170901095247.GY2598@lahna.fi.intel.com \
--to=mika.westerberg@linux.intel.com \
--cc=bmeng.cn@gmail.com \
--cc=boris.brezillon@free-electrons.com \
--cc=computersforpeace@gmail.com \
--cc=cyrille.pitchen@wedev4u.fr \
--cc=dwmw2@infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=marek.vasut@gmail.com \
--cc=richard@nod.at \
--cc=sr@denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
Powered by JetHome