From: <mike.travis@hpe.com>
To: Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
Thomas Gleixner <tglx@linutronix.de>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>,
Bin Gao <bin.gao@linux.intel.com>,
Prarit Bhargava <prarit@redhat.com>,
Dimitri Sivanich <dimitri.sivanich@hpe.com>,
Andrew Banman <andrew.banman@hpe.com>,
Russ Anderson <russ.anderson@hpe.com>,
linux-kernel@vger.kernel.org, x86@kernel.org
Subject: [PATCH 0/3] x86/platform/UV: Update TSC support
Date: Thu, 21 Sep 2017 15:12:21 -0500 [thread overview]
Message-ID: <20170921201221.869441567@stormcage.americas.sgi.com> (raw)
The UV BIOS goes to considerable effort to get the TSC synchronization
accurate across the entire system. Included in that are multiple
chassis that can have 32+ sockets. The architecture also supports an
external high resolution clock to help all the chassis and CPU's in
maintaining this synchronization.
As a result the UV system BIOS provides much better TSC accuracy than
the current kernel TSC ADJUST functions. This is extremely important in
applications that, for example, store and access data bases.
These two patches disable an assumption made by the kernel TSC ADJUST
functions that are not applicable to the UV system (and maybe others?).
That being that Socket 0 in the system should have a TSC ADJUST value
of zero. This is incorrect when all the chassis are started asynchronously
to each other, therefore which TSC's are farther advanced is not predictable.
The UV BIOS deals with this scenario correctly.
--
next reply other threads:[~2017-09-21 20:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-21 20:12 mike.travis [this message]
2017-09-21 20:12 ` [PATCH 1/3] x86/kernel: Add option that TSC on Socket 0 being non-null is valid mike.travis
2017-09-25 15:30 ` Thomas Gleixner
2017-09-25 16:47 ` Mike Travis
2017-09-25 18:10 ` Thomas Gleixner
2017-09-26 0:13 ` Mike Travis
2017-09-26 7:28 ` Thomas Gleixner
2017-09-21 20:12 ` [PATCH 2/3] x86/kernel: Skip TSC test and error messages if already unstable mike.travis
2017-09-21 20:12 ` [PATCH 3/3] x86/platform/UV: Add check of TSC state set by UV BIOS mike.travis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20170921201221.869441567@stormcage.americas.sgi.com \
--to=mike.travis@hpe.com \
--cc=a.p.zijlstra@chello.nl \
--cc=andrew.banman@hpe.com \
--cc=bin.gao@linux.intel.com \
--cc=dimitri.sivanich@hpe.com \
--cc=hpa@zytor.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@redhat.com \
--cc=prarit@redhat.com \
--cc=russ.anderson@hpe.com \
--cc=tglx@linutronix.de \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®