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From: <mike.travis@hpe.com>
To: Peter Zijlstra <peterz@infradead.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>
Cc: Bin Gao <bin.gao@linux.intel.com>,
	Prarit Bhargava <prarit@redhat.com>,
	Dimitri Sivanich <dimitri.sivanich@hpe.com>,
	Andrew Banman <andrew.banman@hpe.com>,
	Russ Anderson <russ.anderson@hpe.com>,
	linux-kernel@vger.kernel.org, x86@kernel.org
Subject: [PATCH 4/5] x86/kernel: Provide a means to disable TSC ART
Date: Mon, 02 Oct 2017 10:12:18 -0500	[thread overview]
Message-ID: <20171002151217.095807201@stormcage.americas.sgi.com> (raw)
In-Reply-To: <20171002151214.822224274@stormcage.americas.sgi.com>

[-- Attachment #1: disable-detect_art --]
[-- Type: text/plain, Size: 1804 bytes --]

On systems where multiple chassis are reset asynchronously there is not a
constant ratio between the ART frequency and the TSC time that can be
provided by the boot cpu.  Provide a means to disable the ART capability
by arches that have this characteristic.

Signed-off-by: Mike Travis <mike.travis@hpe.com>
---
 arch/x86/include/asm/tsc.h |    1 +
 arch/x86/kernel/tsc.c      |   16 +++++++++++++---
 2 files changed, 14 insertions(+), 3 deletions(-)

--- linux.orig/arch/x86/include/asm/tsc.h
+++ linux/arch/x86/include/asm/tsc.h
@@ -36,6 +36,7 @@ extern void mark_tsc_unstable(char *reas
 extern int unsynchronized_tsc(void);
 extern int check_tsc_unstable(void);
 extern void mark_tsc_multi_sync_resets(char *reason);
+extern void mark_tsc_art_disabled(char *reason);
 extern unsigned long native_calibrate_cpu(void);
 extern unsigned long native_calibrate_tsc(void);
 extern unsigned long long native_sched_clock_from_tsc(u64 tsc);
--- linux.orig/arch/x86/kernel/tsc.c
+++ linux/arch/x86/kernel/tsc.c
@@ -955,15 +955,25 @@ core_initcall(cpufreq_register_tsc_scali
 #define ART_CPUID_LEAF (0x15)
 #define ART_MIN_DENOMINATOR (1)
 
-
 /*
- * If ART is present detect the numerator:denominator to convert to TSC
+ * If ART is present detect the numerator:denominator to convert to TSC.
+ * The CPU ART capability can be disabled.
  */
+static bool tsc_art_disabled;
+
+void mark_tsc_art_disabled(char *reason)
+{
+	if (tsc_art_disabled)
+		return;
+	tsc_art_disabled = true;
+	pr_info("TSC: ART disabled due to %s\n", reason);
+}
+
 static void detect_art(void)
 {
 	unsigned int unused[2];
 
-	if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF)
+	if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF || tsc_art_disabled)
 		return;
 
 	/* Don't enable ART in a VM, non-stop TSC and TSC_ADJUST required */

-- 

  parent reply	other threads:[~2017-10-02 15:13 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-10-02 15:12 [PATCH 0/5] x86/platform/UV: Update TSC support mike.travis
2017-10-02 15:12 ` [PATCH 1/5] x86/kernel: Add option that TSC on Socket 0 being non-zero is valid mike.travis
2017-10-02 15:12 ` [PATCH 2/5] x86/kernel: Skip TSC test and error messages if already unstable mike.travis
2017-10-02 15:12 ` [PATCH 3/5] x86/kernel: Drastically reduce the number of firmware bug warnings mike.travis
2017-10-02 15:12 ` mike.travis [this message]
2017-10-04  9:27   ` [PATCH 4/5] x86/kernel: Provide a means to disable TSC ART Peter Zijlstra
2017-10-04 14:15     ` Mike Travis
2017-10-04 18:50       ` Thomas Gleixner
2017-10-02 15:12 ` [PATCH 5/5] x86/platform/UV: Add check of TSC state set by UV BIOS mike.travis
2017-10-05 16:47 [PATCH 0/5] x86/platform/UV: Update TSC support mike.travis
2017-10-05 16:47 ` [PATCH 4/5] x86/kernel: Provide a means to disable TSC ART mike.travis
2017-10-12 16:32 [PATCH 0/5] x86/platform/UV: Update TSC support mike.travis
2017-10-12 16:32 ` [PATCH 4/5] x86/kernel: Provide a means to disable TSC ART mike.travis

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