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From: Alex Williamson <alex.williamson@redhat.com>
To: Gary R Hook <gary.hook@amd.com>
Cc: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] iommu/amd - Set the device table entry PPR bit for IOMMU V2 devices
Date: Wed, 20 Dec 2017 12:02:51 -0700	[thread overview]
Message-ID: <20171220120251.435ed475@t450s.home> (raw)
In-Reply-To: <151372174181.127118.3644062052273990281.stgit@sosxen2.amd.com>

On Tue, 19 Dec 2017 16:15:41 -0600
Gary R Hook <gary.hook@amd.com> wrote:

> The AMD IOMMU specification Rev 3.00 (December 2016) introduces a
> new Enhanced PPR Handling Support (EPHSup) bit in the MMIO register
> offset 0030h (IOMMU Extended Feature Register).
> 
> When EPHSup=1, the IOMMU hardware requires the PPR bit of the
> device table entry (DTE) to be set in order to support PPR for a
> particular endpoint device.
> 
> Please see https://support.amd.com/TechDocs/48882_IOMMU.pdf for
> this revision of the AMD IOMMU specification.
> 
> Signed-off-by: Gary R Hook <gary.hook@amd.com>
> ---
>  0 files changed

Hmm, something funky there, but looks fine otherwise.  Applied to
v4.16-iommu/amd.  Thanks,

Alex

  reply	other threads:[~2017-12-20 19:02 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-12-19 22:15 Gary R Hook
2017-12-20 19:02 ` Alex Williamson [this message]
2017-12-20 19:50   ` Gary R Hook

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