* [PATCH 0/2] Add EHCI/OHCI nodes for V3s and Lichee Pi Zero
@ 2017-12-21 15:05 Icenowy Zheng
2017-12-21 15:05 ` [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes Icenowy Zheng
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Icenowy Zheng @ 2017-12-21 15:05 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng
As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes
are now necessary.
Please apply these patches to 4.15, Thanks!
Icenowy Zheng (2):
ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
2 files changed, 27 insertions(+)
--
2.14.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
2017-12-21 15:05 [PATCH 0/2] Add EHCI/OHCI nodes for V3s and Lichee Pi Zero Icenowy Zheng
@ 2017-12-21 15:05 ` Icenowy Zheng
2017-12-21 15:16 ` Maxime Ripard
2017-12-21 15:22 ` Maxime Ripard
2017-12-21 15:05 ` [PATCH 2/2] ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero Icenowy Zheng
2017-12-21 15:21 ` [PATCH 0/2] Add EHCI/OHCI nodes for V3s and " Maxime Ripard
2 siblings, 2 replies; 6+ messages in thread
From: Icenowy Zheng @ 2017-12-21 15:05 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 443b083c6adc..cc315dc742d2 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -264,6 +264,25 @@
#phy-cells = <1>;
};
+ ehci0: usb@01c1a000 {
+ compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb@01c1a400 {
+ compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ccu: clock@1c20000 {
compatible = "allwinner,sun8i-v3s-ccu";
reg = <0x01c20000 0x400>;
--
2.14.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
2017-12-21 15:05 [PATCH 0/2] Add EHCI/OHCI nodes for V3s and Lichee Pi Zero Icenowy Zheng
2017-12-21 15:05 ` [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes Icenowy Zheng
@ 2017-12-21 15:05 ` Icenowy Zheng
2017-12-21 15:21 ` [PATCH 0/2] Add EHCI/OHCI nodes for V3s and " Maxime Ripard
2 siblings, 0 replies; 6+ messages in thread
From: Icenowy Zheng @ 2017-12-21 15:05 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-sunxi, Icenowy Zheng
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
index 387fc2aa546d..cf2d9fe3bbb7 100644
--- a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -77,6 +77,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-0 = <&mmc0_pins_a>;
pinctrl-names = "default";
@@ -86,6 +90,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-0 = <&uart0_pins_a>;
pinctrl-names = "default";
--
2.14.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
2017-12-21 15:05 ` [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes Icenowy Zheng
@ 2017-12-21 15:16 ` Maxime Ripard
2017-12-21 15:22 ` Maxime Ripard
1 sibling, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2017-12-21 15:16 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 1555 bytes --]
Hi,
On Thu, Dec 21, 2017 at 11:05:36PM +0800, Icenowy Zheng wrote:
> The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
> controllers.
>
> Add the device nodes for the controllers.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index 443b083c6adc..cc315dc742d2 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -264,6 +264,25 @@
> #phy-cells = <1>;
> };
>
> + ehci0: usb@01c1a000 {
> + compatible = "allwinner,sun8i-v3s-ehci", "generic-ehci";
> + reg = <0x01c1a000 0x100>;
> + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
> + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
Why are you taking the OHCI clocks and resets in the OHCI node..
> + status = "disabled";
> + };
> +
> + ohci0: usb@01c1a400 {
> + compatible = "allwinner,sun8i-v3s-ohci", "generic-ohci";
> + reg = <0x01c1a400 0x100>;
> + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
... And the EHCI clocks and resets in the OHCI node?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Add EHCI/OHCI nodes for V3s and Lichee Pi Zero
2017-12-21 15:05 [PATCH 0/2] Add EHCI/OHCI nodes for V3s and Lichee Pi Zero Icenowy Zheng
2017-12-21 15:05 ` [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes Icenowy Zheng
2017-12-21 15:05 ` [PATCH 2/2] ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero Icenowy Zheng
@ 2017-12-21 15:21 ` Maxime Ripard
2 siblings, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2017-12-21 15:21 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 446 bytes --]
On Thu, Dec 21, 2017 at 11:05:35PM +0800, Icenowy Zheng wrote:
> As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes
> are now necessary.
>
> Please apply these patches to 4.15, Thanks!
There's no reason to have it merged in 4.15. It's not a regression,
so 4.15 should work just as 4.14 worked, right?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
2017-12-21 15:05 ` [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes Icenowy Zheng
2017-12-21 15:16 ` Maxime Ripard
@ 2017-12-21 15:22 ` Maxime Ripard
1 sibling, 0 replies; 6+ messages in thread
From: Maxime Ripard @ 2017-12-21 15:22 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Chen-Yu Tsai, devicetree, linux-arm-kernel, linux-kernel, linux-sunxi
[-- Attachment #1: Type: text/plain, Size: 857 bytes --]
On Thu, Dec 21, 2017 at 11:05:36PM +0800, Icenowy Zheng wrote:
> The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
> controllers.
>
> Add the device nodes for the controllers.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index 443b083c6adc..cc315dc742d2 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -264,6 +264,25 @@
> #phy-cells = <1>;
> };
>
> + ehci0: usb@01c1a000 {
And you should also drop the leading zero on your two nodes
unit-address.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2017-12-21 15:22 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2017-12-21 15:05 [PATCH 0/2] Add EHCI/OHCI nodes for V3s and Lichee Pi Zero Icenowy Zheng
2017-12-21 15:05 ` [PATCH 1/2] ARM: sun8i: v3s: add EHCI/OHCI0 device nodes Icenowy Zheng
2017-12-21 15:16 ` Maxime Ripard
2017-12-21 15:22 ` Maxime Ripard
2017-12-21 15:05 ` [PATCH 2/2] ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero Icenowy Zheng
2017-12-21 15:21 ` [PATCH 0/2] Add EHCI/OHCI nodes for V3s and " Maxime Ripard
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