* [PATCH v11 0/3] arm: npcm: add basic support for Nuvoton BMCs
@ 2018-02-16 2:40 Brendan Higgins
2018-02-16 2:40 ` [PATCH v11 1/3] " Brendan Higgins
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Brendan Higgins @ 2018-02-16 2:40 UTC (permalink / raw)
To: robh+dt, linux, mark.rutland, tmaimon77, avifishman70,
julien.thierry, pombredanne, arnd, olof, khilman
Cc: devicetree, openbmc, linux-kernel, linux-arm-kernel
Addressed comments from:
- Arnd: https://www.spinics.net/lists/arm-kernel/msg634442.html
- Joel: https://www.spinics.net/lists/arm-kernel/msg634554.html
Summary of changes since previous update:
- More device tree and binding doc clean up.
All changes tested on Nuvoton NPCM750 EVB.
I went ahead and decided to submit a pull request to Arnd, Olof, and
Kevin, as requested since I figured that we were about at the end of
feedback and we want to get this in.
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v11 1/3] arm: npcm: add basic support for Nuvoton BMCs 2018-02-16 2:40 [PATCH v11 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins @ 2018-02-16 2:40 ` Brendan Higgins 2018-02-16 2:40 ` [PATCH v11 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins 2018-02-16 2:40 ` [PATCH v11 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture Brendan Higgins 2 siblings, 0 replies; 5+ messages in thread From: Brendan Higgins @ 2018-02-16 2:40 UTC (permalink / raw) To: robh+dt, linux, mark.rutland, tmaimon77, avifishman70, julien.thierry, pombredanne, arnd, olof, khilman Cc: devicetree, openbmc, linux-kernel, linux-arm-kernel, Brendan Higgins Adds basic support for the Nuvoton NPCM750 BMC. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> --- arch/arm/Kconfig | 2 + arch/arm/Makefile | 1 + arch/arm/mach-npcm/Kconfig | 48 +++++++++++++++++++++ arch/arm/mach-npcm/Makefile | 3 ++ arch/arm/mach-npcm/headsmp.S | 17 ++++++++ arch/arm/mach-npcm/npcm7xx.c | 20 +++++++++ arch/arm/mach-npcm/platsmp.c | 81 ++++++++++++++++++++++++++++++++++++ 7 files changed, 172 insertions(+) create mode 100644 arch/arm/mach-npcm/Kconfig create mode 100644 arch/arm/mach-npcm/Makefile create mode 100644 arch/arm/mach-npcm/headsmp.S create mode 100644 arch/arm/mach-npcm/npcm7xx.c create mode 100644 arch/arm/mach-npcm/platsmp.c diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7e3d53575486..6a8404cd5150 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -779,6 +779,8 @@ source "arch/arm/mach-netx/Kconfig" source "arch/arm/mach-nomadik/Kconfig" +source "arch/arm/mach-npcm/Kconfig" + source "arch/arm/mach-nspire/Kconfig" source "arch/arm/plat-omap/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index e83f5161fdd8..e4e537f27339 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -196,6 +196,7 @@ machine-$(CONFIG_ARCH_MEDIATEK) += mediatek machine-$(CONFIG_ARCH_MXS) += mxs machine-$(CONFIG_ARCH_NETX) += netx machine-$(CONFIG_ARCH_NOMADIK) += nomadik +machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_NSPIRE) += nspire machine-$(CONFIG_ARCH_OXNAS) += oxnas machine-$(CONFIG_ARCH_OMAP1) += omap1 diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig new file mode 100644 index 000000000000..6ff9df2636be --- /dev/null +++ b/arch/arm/mach-npcm/Kconfig @@ -0,0 +1,48 @@ +menuconfig ARCH_NPCM + bool "Nuvoton NPCM Architecture" + select ARCH_REQUIRE_GPIOLIB + select USE_OF + select PINCTRL + select PINCTRL_NPCM7XX + +if ARCH_NPCM + +comment "NPCM7XX CPU type" + +config ARCH_NPCM750 + depends on ARCH_NPCM && ARCH_MULTI_V7 + bool "Support for NPCM750 BMC CPU (Poleg)" + select CACHE_L2X0 + select CPU_V7 + select ARM_GIC + select HAVE_SMP + select SMP + select SMP_ON_UP + select HAVE_ARM_SCU + select HAVE_ARM_TWD if SMP + select ARM_ERRATA_720789 + select ARM_ERRATA_754322 + select ARM_ERRATA_764369 + select ARM_ERRATA_794072 + select PL310_ERRATA_588369 + select PL310_ERRATA_727915 + select USB_EHCI_ROOT_HUB_TT + select USB_ARCH_HAS_HCD + select USB_ARCH_HAS_EHCI + select USB_EHCI_HCD + select USB_ARCH_HAS_OHCI + select USB_OHCI_HCD + select USB + select FIQ + select CPU_USE_DOMAINS + select GENERIC_CLOCKEVENTS + select CLKDEV_LOOKUP + select COMMON_CLK if OF + select NPCM750_TIMER + select MFD_SYSCON + help + Support for NPCM750 BMC CPU (Poleg). + + Nuvoton NPCM750 BMC based on the Cortex A9. + +endif diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile new file mode 100644 index 000000000000..c7a1316d27c1 --- /dev/null +++ b/arch/arm/mach-npcm/Makefile @@ -0,0 +1,3 @@ +AFLAGS_headsmp.o += -march=armv7-a + +obj-$(CONFIG_ARCH_NPCM750) += npcm7xx.o platsmp.o headsmp.o diff --git a/arch/arm/mach-npcm/headsmp.S b/arch/arm/mach-npcm/headsmp.S new file mode 100644 index 000000000000..c083fe09a07b --- /dev/null +++ b/arch/arm/mach-npcm/headsmp.S @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright 2018 Google, Inc. + +#include <linux/linkage.h> +#include <linux/init.h> +#include <asm/assembler.h> + +/* + * The boot ROM does not start secondary CPUs in SVC mode, so we need to do that + * here. + */ +ENTRY(npcm7xx_secondary_startup) + safe_svcmode_maskall r0 + + b secondary_startup +ENDPROC(npcm7xx_secondary_startup) diff --git a/arch/arm/mach-npcm/npcm7xx.c b/arch/arm/mach-npcm/npcm7xx.c new file mode 100644 index 000000000000..5f7cd88103ef --- /dev/null +++ b/arch/arm/mach-npcm/npcm7xx.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright 2018 Google, Inc. + +#include <linux/kernel.h> +#include <linux/types.h> +#include <asm/mach/arch.h> +#include <asm/mach-types.h> +#include <asm/mach/map.h> +#include <asm/hardware/cache-l2x0.h> + +static const char *const npcm7xx_dt_match[] = { + "nuvoton,npcm750", + NULL +}; + +DT_MACHINE_START(NPCM7XX_DT, "NPCM7XX Chip family") + .atag_offset = 0x100, + .dt_compat = npcm7xx_dt_match, +MACHINE_END diff --git a/arch/arm/mach-npcm/platsmp.c b/arch/arm/mach-npcm/platsmp.c new file mode 100644 index 000000000000..21633c70fe7f --- /dev/null +++ b/arch/arm/mach-npcm/platsmp.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright 2018 Google, Inc. + +#define pr_fmt(fmt) "nuvoton,npcm7xx-smp: " fmt + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/smp.h> +#include <linux/io.h> +#include <linux/of.h> +#include <linux/of_device.h> +#include <linux/of_platform.h> +#include <linux/of_address.h> +#include <asm/cacheflush.h> +#include <asm/smp.h> +#include <asm/smp_plat.h> +#include <asm/smp_scu.h> + +#define NPCM7XX_SCRPAD_REG 0x13c + +extern void npcm7xx_secondary_startup(void); + +static int npcm7xx_smp_boot_secondary(unsigned int cpu, + struct task_struct *idle) +{ + struct device_node *gcr_np; + void __iomem *gcr_base; + int ret = 0; + + gcr_np = of_find_compatible_node(NULL, NULL, "nuvoton,npcm750-gcr"); + if (!gcr_np) { + pr_err("no gcr device node\n"); + ret = -ENODEV; + goto out; + } + gcr_base = of_iomap(gcr_np, 0); + if (!gcr_base) { + pr_err("could not iomap gcr"); + ret = -ENOMEM; + goto out; + } + + /* give boot ROM kernel start address. */ + iowrite32(__pa_symbol(npcm7xx_secondary_startup), gcr_base + + NPCM7XX_SCRPAD_REG); + /* make sure the previous write is seen by all observers. */ + dsb_sev(); + + iounmap(gcr_base); +out: + return ret; +} + +static void __init npcm7xx_smp_prepare_cpus(unsigned int max_cpus) +{ + struct device_node *scu_np; + void __iomem *scu_base; + + scu_np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu"); + if (!scu_np) { + pr_err("no scu device node\n"); + return; + } + scu_base = of_iomap(scu_np, 0); + if (!scu_base) { + pr_err("could not iomap scu"); + return; + } + + scu_enable(scu_base); + + iounmap(scu_base); +} + +static struct smp_operations npcm7xx_smp_ops __initdata = { + .smp_prepare_cpus = npcm7xx_smp_prepare_cpus, + .smp_boot_secondary = npcm7xx_smp_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(npcm7xx_smp, "nuvoton,npcm750-smp", &npcm7xx_smp_ops); -- 2.16.1.291.g4437f3f132-goog ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v11 2/3] arm: dts: add Nuvoton NPCM750 device tree 2018-02-16 2:40 [PATCH v11 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins 2018-02-16 2:40 ` [PATCH v11 1/3] " Brendan Higgins @ 2018-02-16 2:40 ` Brendan Higgins 2018-03-12 15:23 ` Tomer Maimon 2018-02-16 2:40 ` [PATCH v11 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture Brendan Higgins 2 siblings, 1 reply; 5+ messages in thread From: Brendan Higgins @ 2018-02-16 2:40 UTC (permalink / raw) To: robh+dt, linux, mark.rutland, tmaimon77, avifishman70, julien.thierry, pombredanne, arnd, olof, khilman Cc: devicetree, openbmc, linux-kernel, linux-arm-kernel, Brendan Higgins Add a common device tree for all Nuvoton NPCM750 BMCs and a board specific device tree for the NPCM750 (Poleg) evaluation board. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Tested-by: Tomer Maimon <tmaimon77@gmail.com> Tested-by: Avi Fishman <avifishman70@gmail.com> Tested-by: Joel Stanley <joel@jms.id.au> --- .../arm/cpu-enable-method/nuvoton,npcm750-smp | 42 +++++ .../devicetree/bindings/arm/npcm/npcm.txt | 6 + arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 35 ++++ arch/arm/boot/dts/nuvoton-npcm750.dtsi | 165 ++++++++++++++++++ 5 files changed, 250 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp new file mode 100644 index 000000000000..8e043301e28e --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp @@ -0,0 +1,42 @@ +========================================================= +Secondary CPU enable-method "nuvoton,npcm750-smp" binding +========================================================= + +To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be +defined in the "cpus" node. + +Enable method name: "nuvoton,npcm750-smp" +Compatible machines: "nuvoton,npcm750" +Compatible CPUs: "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"nuvoton,npcm750-gcr". + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&L2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk NPCM7XX_CLK_CPU>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt new file mode 100644 index 000000000000..2d87d9ecea85 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt @@ -0,0 +1,6 @@ +NPCM Platforms Device Tree Bindings +----------------------------------- +NPCM750 SoC +Required root node properties: + - compatible = "nuvoton,npcm750"; + diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index ade7a38543dc..eeab5dac50ab 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -304,6 +304,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \ dtb-$(CONFIG_ARCH_LPC32XX) += \ lpc3250-ea3250.dtb \ lpc3250-phy3250.dtb +dtb-$(CONFIG_ARCH_NPCM750) += \ + nuvoton-npcm750-evb.dtb dtb-$(CONFIG_MACH_MESON6) += \ meson6-atv1200.dtb dtb-$(CONFIG_MACH_MESON8) += \ diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts new file mode 100644 index 000000000000..cabde3d5be8a --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright 2018 Google, Inc. + +/dts-v1/; +#include "nuvoton-npcm750.dtsi" + +/ { + model = "Nuvoton npcm750 Development Board (Device Tree)"; + compatible = "nuvoton,npcm750"; + + chosen { + stdout-path = &serial3; + }; + + memory { + reg = <0 0x40000000>; + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi new file mode 100644 index 000000000000..839e45cfd695 --- /dev/null +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Nuvoton Technology corporation. +// Copyright 2018 Google, Inc. + +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "nuvoton,npcm750-smp"; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk 10>; + clock-names = "clk_cpu"; + reg = <0>; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + clocks = <&clk 10>; + clock-names = "clk_cpu"; + reg = <1>; + next-level-cache = <&l2>; + }; + }; + + /* external clock signal rg1refck, supplied by the phy */ + clk-rg1refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + /* external clock signal rg2refck, supplied by the phy */ + clk-rg2refck { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + clk-xin { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00900000>; + + gcr: gcr@800000 { + compatible = "nuvoton,npcm750-gcr", "syscon", + "simple-mfd"; + reg = <0x800000 0x1000>; + }; + + scu: scu@3fe000 { + compatible = "arm,cortex-a9-scu"; + reg = <0x3fe000 0x1000>; + }; + + l2: cache-controller@3fc000 { + compatible = "arm,pl310-cache"; + reg = <0x3fc000 0x1000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + cache-unified; + cache-level = <2>; + clocks = <&clk 22>; + arm,shared-override; + }; + + gic: interrupt-controller@3ff000 { + compatible = "arm,cortex-a9-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x3ff000 0x1000>, + <0x3fe100 0x100>; + }; + + timer@3fe600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x3fe600 0x20>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | + IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&clk 15>; + }; + }; + + ahb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges; + + clk: clock-controller@f0801000 { + compatible = "nuvoton,npcm750-clk"; + #clock-cells = <1>; + reg = <0xf0801000 0x1000>; + }; + + apb { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&gic>; + ranges = <0x0 0xf0000000 0x00300000>; + + timer0: timer@8000 { + compatible = "nuvoton,npcm750-timer"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x8000 0x1000>; + clocks = <&clk 15>; + }; + + serial0: serial@1000 { + compatible = "ns16550a"; + reg = <0x1000 0x1000>; + clocks = <&clk 14>; + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + status = "disabled"; + }; + + serial1: serial@2000 { + compatible = "ns16550a"; + reg = <0x2000 0x1000>; + clocks = <&clk 14>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + status = "disabled"; + }; + + serial2: serial@3000 { + compatible = "ns16550a"; + reg = <0x3000 0x1000>; + clocks = <&clk 14>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + status = "disabled"; + }; + + serial3: serial@4000 { + compatible = "ns16550a"; + reg = <0x4000 0x1000>; + clocks = <&clk 14>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + reg-shift = <2>; + status = "disabled"; + }; + }; + }; +}; -- 2.16.1.291.g4437f3f132-goog ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v11 2/3] arm: dts: add Nuvoton NPCM750 device tree 2018-02-16 2:40 ` [PATCH v11 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins @ 2018-03-12 15:23 ` Tomer Maimon 0 siblings, 0 replies; 5+ messages in thread From: Tomer Maimon @ 2018-03-12 15:23 UTC (permalink / raw) To: Brendan Higgins Cc: Rob Herring, Russell King - ARM Linux, Mark Rutland, Avi Fishman, julien.thierry, pombredanne, Arnd Bergmann, olof, khilman, devicetree, OpenBMC Maillist, Linux Kernel Mailing List, Linux ARM On 16 February 2018 at 04:40, Brendan Higgins <brendanhiggins@google.com> wrote: > Add a common device tree for all Nuvoton NPCM750 BMCs and a board > specific device tree for the NPCM750 (Poleg) evaluation board. > > Signed-off-by: Brendan Higgins <brendanhiggins@google.com> > Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> > Reviewed-by: Avi Fishman <avifishman70@gmail.com> > Reviewed-by: Joel Stanley <joel@jms.id.au> > Reviewed-by: Rob Herring <robh@kernel.org> > Tested-by: Tomer Maimon <tmaimon77@gmail.com> > Tested-by: Avi Fishman <avifishman70@gmail.com> > Tested-by: Joel Stanley <joel@jms.id.au> > --- > .../arm/cpu-enable-method/nuvoton,npcm750-smp | 42 +++++ > .../devicetree/bindings/arm/npcm/npcm.txt | 6 + > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/nuvoton-npcm750-evb.dts | 35 ++++ > arch/arm/boot/dts/nuvoton-npcm750.dtsi | 165 ++++++++++++++++++ > 5 files changed, 250 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp > create mode 100644 Documentation/devicetree/bindings/arm/npcm/npcm.txt > create mode 100644 arch/arm/boot/dts/nuvoton-npcm750-evb.dts > create mode 100644 arch/arm/boot/dts/nuvoton-npcm750.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp > new file mode 100644 > index 000000000000..8e043301e28e > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/nuvoton,npcm750-smp > @@ -0,0 +1,42 @@ Rob, if will like to add new chip to enable the SMP (NPCM730). what will be the best way to add it to the binding documentation file? 1. Do I need to add new binding file nuvoton,npcm730-smp? 2. Add nuvoton,npcm730-smp option to the current nuvoton,npcm750-smp file? 3. Modify the nuvoton,npcm750-smp binding name to nuvoton,npcm7xx-smp and to describe both chips in it. > +========================================================= > +Secondary CPU enable-method "nuvoton,npcm750-smp" binding > +========================================================= > + > +To apply to all CPUs, a single "nuvoton,npcm750-smp" enable method should be > +defined in the "cpus" node. > + > +Enable method name: "nuvoton,npcm750-smp" > +Compatible machines: "nuvoton,npcm750" > +Compatible CPUs: "arm,cortex-a9" > +Related properties: (none) > + > +Note: > +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and > +"nuvoton,npcm750-gcr". > + > +Example: > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm750-smp"; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&L2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk NPCM7XX_CLK_CPU>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&L2>; > + }; > + }; > + > diff --git a/Documentation/devicetree/bindings/arm/npcm/npcm.txt b/Documentation/devicetree/bindings/arm/npcm/npcm.txt > new file mode 100644 > index 000000000000..2d87d9ecea85 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/npcm/npcm.txt > @@ -0,0 +1,6 @@ > +NPCM Platforms Device Tree Bindings > +----------------------------------- > +NPCM750 SoC > +Required root node properties: > + - compatible = "nuvoton,npcm750"; > + > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index ade7a38543dc..eeab5dac50ab 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -304,6 +304,8 @@ dtb-$(CONFIG_ARCH_LPC18XX) += \ > dtb-$(CONFIG_ARCH_LPC32XX) += \ > lpc3250-ea3250.dtb \ > lpc3250-phy3250.dtb > +dtb-$(CONFIG_ARCH_NPCM750) += \ > + nuvoton-npcm750-evb.dtb > dtb-$(CONFIG_MACH_MESON6) += \ > meson6-atv1200.dtb > dtb-$(CONFIG_MACH_MESON8) += \ > diff --git a/arch/arm/boot/dts/nuvoton-npcm750-evb.dts b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts > new file mode 100644 > index 000000000000..cabde3d5be8a > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm750-evb.dts > @@ -0,0 +1,35 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2018 Nuvoton Technology corporation. > +// Copyright 2018 Google, Inc. > + > +/dts-v1/; > +#include "nuvoton-npcm750.dtsi" > + > +/ { > + model = "Nuvoton npcm750 Development Board (Device Tree)"; > + compatible = "nuvoton,npcm750"; > + > + chosen { > + stdout-path = &serial3; > + }; > + > + memory { > + reg = <0 0x40000000>; > + }; > +}; > + > +&serial0 { > + status = "okay"; > +}; > + > +&serial1 { > + status = "okay"; > +}; > + > +&serial2 { > + status = "okay"; > +}; > + > +&serial3 { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/nuvoton-npcm750.dtsi b/arch/arm/boot/dts/nuvoton-npcm750.dtsi > new file mode 100644 > index 000000000000..839e45cfd695 > --- /dev/null > +++ b/arch/arm/boot/dts/nuvoton-npcm750.dtsi > @@ -0,0 +1,165 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2018 Nuvoton Technology corporation. > +// Copyright 2018 Google, Inc. > + > +#include <dt-bindings/interrupt-controller/arm-gic.h> > + > +/ { > + #address-cells = <1>; > + #size-cells = <1>; > + interrupt-parent = <&gic>; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + enable-method = "nuvoton,npcm750-smp"; > + > + cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk 10>; > + clock-names = "clk_cpu"; > + reg = <0>; > + next-level-cache = <&l2>; > + }; > + > + cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a9"; > + clocks = <&clk 10>; > + clock-names = "clk_cpu"; > + reg = <1>; > + next-level-cache = <&l2>; > + }; > + }; > + > + /* external clock signal rg1refck, supplied by the phy */ > + clk-rg1refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > + > + /* external clock signal rg2refck, supplied by the phy */ > + clk-rg2refck { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > + > + clk-xin { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <50000000>; > + }; > + > + soc { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges = <0x0 0xf0000000 0x00900000>; > + > + gcr: gcr@800000 { > + compatible = "nuvoton,npcm750-gcr", "syscon", > + "simple-mfd"; > + reg = <0x800000 0x1000>; > + }; > + > + scu: scu@3fe000 { > + compatible = "arm,cortex-a9-scu"; > + reg = <0x3fe000 0x1000>; > + }; > + > + l2: cache-controller@3fc000 { > + compatible = "arm,pl310-cache"; > + reg = <0x3fc000 0x1000>; > + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; > + cache-unified; > + cache-level = <2>; > + clocks = <&clk 22>; > + arm,shared-override; > + }; > + > + gic: interrupt-controller@3ff000 { > + compatible = "arm,cortex-a9-gic"; > + interrupt-controller; > + #interrupt-cells = <3>; > + reg = <0x3ff000 0x1000>, > + <0x3fe100 0x100>; > + }; > + > + timer@3fe600 { > + compatible = "arm,cortex-a9-twd-timer"; > + reg = <0x3fe600 0x20>; > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | > + IRQ_TYPE_LEVEL_HIGH)>; > + clocks = <&clk 15>; > + }; > + }; > + > + ahb { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges; > + > + clk: clock-controller@f0801000 { > + compatible = "nuvoton,npcm750-clk"; > + #clock-cells = <1>; > + reg = <0xf0801000 0x1000>; > + }; > + > + apb { > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "simple-bus"; > + interrupt-parent = <&gic>; > + ranges = <0x0 0xf0000000 0x00300000>; > + > + timer0: timer@8000 { > + compatible = "nuvoton,npcm750-timer"; > + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; > + reg = <0x8000 0x1000>; > + clocks = <&clk 15>; > + }; > + > + serial0: serial@1000 { > + compatible = "ns16550a"; > + reg = <0x1000 0x1000>; > + clocks = <&clk 14>; > + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial1: serial@2000 { > + compatible = "ns16550a"; > + reg = <0x2000 0x1000>; > + clocks = <&clk 14>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial2: serial@3000 { > + compatible = "ns16550a"; > + reg = <0x3000 0x1000>; > + clocks = <&clk 14>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + > + serial3: serial@4000 { > + compatible = "ns16550a"; > + reg = <0x4000 0x1000>; > + clocks = <&clk 14>; > + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + reg-shift = <2>; > + status = "disabled"; > + }; > + }; > + }; > +}; > -- > 2.16.1.291.g4437f3f132-goog > Thanks, Tomer ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v11 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture 2018-02-16 2:40 [PATCH v11 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins 2018-02-16 2:40 ` [PATCH v11 1/3] " Brendan Higgins 2018-02-16 2:40 ` [PATCH v11 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins @ 2018-02-16 2:40 ` Brendan Higgins 2 siblings, 0 replies; 5+ messages in thread From: Brendan Higgins @ 2018-02-16 2:40 UTC (permalink / raw) To: robh+dt, linux, mark.rutland, tmaimon77, avifishman70, julien.thierry, pombredanne, arnd, olof, khilman Cc: devicetree, openbmc, linux-kernel, linux-arm-kernel, Brendan Higgins Add maintainers and reviewers for the Nuvoton NPCM architecture. Signed-off-by: Brendan Higgins <brendanhiggins@google.com> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> --- MAINTAINERS | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3bdc260e36b7..02d1b0345298 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1700,6 +1700,20 @@ F: Documentation/devicetree/bindings/arm/ste-* F: Documentation/devicetree/bindings/arm/ux500/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git +ARM/NUVOTON NPCM ARCHITECTURE +M: Avi Fishman <avifishman70@gmail.com> +M: Tomer Maimon <tmaimon77@gmail.com> +R: Patrick Venture <venture@google.com> +R: Nancy Yuen <yuenn@google.com> +R: Brendan Higgins <brendanhiggins@google.com> +L: openbmc@lists.ozlabs.org (moderated for non-subscribers) +S: Supported +F: arch/arm/mach-npcm/ +F: arch/arm/boot/dts/nuvoton-npcm* +F: include/dt-bindings/clock/nuvoton,npcm7xx-clks.h +F: drivers/*/*npcm* +F: Documentation/*/*npcm* + ARM/NUVOTON W90X900 ARM ARCHITECTURE M: Wan ZongShun <mcuos.com@gmail.com> L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -- 2.16.1.291.g4437f3f132-goog ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-03-12 15:23 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-02-16 2:40 [PATCH v11 0/3] arm: npcm: add basic support for Nuvoton BMCs Brendan Higgins 2018-02-16 2:40 ` [PATCH v11 1/3] " Brendan Higgins 2018-02-16 2:40 ` [PATCH v11 2/3] arm: dts: add Nuvoton NPCM750 device tree Brendan Higgins 2018-03-12 15:23 ` Tomer Maimon 2018-02-16 2:40 ` [PATCH v11 3/3] MAINTAINERS: Add entry for the Nuvoton NPCM architecture Brendan Higgins
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