From: Alexandre Belloni <alexandre.belloni@bootlin.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Alexander Dahl <ada@thorsis.com>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
Boris Brezillon <boris.brezillon@bootlin.com>,
Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH v3 0/6] clocksource: rework Atmel TCB timer driver
Date: Wed, 28 Mar 2018 17:31:35 +0200 [thread overview]
Message-ID: <20180328153135.GG13942@piout.net> (raw)
In-Reply-To: <75e5917b-a9ba-c67e-e964-3f002681f9bb@linaro.org>
On 28/03/2018 at 16:36:34 +0200, Daniel Lezcano wrote:
> On 28/03/2018 16:16, Alexandre Belloni wrote:
> > On 28/03/2018 at 15:03:11 +0200, Daniel Lezcano wrote:
> >> On 28/03/2018 12:29, Alexander Dahl wrote:
> >>> Hello Daniel,
> >>>
> >>> Am Dienstag, 27. März 2018, 13:30:22 CEST schrieb Daniel Lezcano:
> >>>> Can you can give a rough amount for the irq rate on the timer ?
> >>>
> >>> I used itop [1] now to get a rough estimate. First with kernel v4.14.29-rt25
> >>> (fully preempt RT):
> >>>
> >>> INT NAME RATE MAX
> >>> 19 [ vel tc_clkevt] 397 Ints/s (max: 432)
> >>> 26 [ vel eth0] 4 Ints/s (max: 38)
> >>>
> >>> Next test with kernel v4.15.13 gives (slightly slower, but non-RT):
> >>>
> >>> INT NAME RATE MAX
> >>> 19 [ vel tc_clkevt] 248 Ints/s (max: 273)
> >>> 26 [ vel eth0] 4 Ints/s (max: 11)
> >>>
> >>> With kernel v4.16-rc7 plus this patch series and tcb as clocksource:
> >>>
> >>> INT NAME RATE MAX
> >>> 17 [vel timer@fffa] 2164 Ints/s (max: 2183)
> >>> 26 [ vel eth0] 5 Ints/s (max: 10)
> >>>
> >>> Is this the information you wanted? If not, could you point me on how to get
> >>> the requested irq rate?
> >>
> >> It is perfect. Thanks!
> >>
> >> It confirms what I was worried about: the clocksource wraps up too
> >> quickly thus raising an interrupt every 400us. That is why I asked
> >> Alexande about a prescalar register.
> >>
> >
> > The code should behave exactly the same between the previous and the new
> > driver. The interrupt is not coming from the clocksource but from the
> > clockevent and it is already on the slowest clock, the 32kHz one.
>
> Do you have an explanation of why the rate is much higher ?
>
The core is giving deltas of 31 clocks instead of much more than that, I
guess I messed up the initialization somewhere.
--
Alexandre Belloni, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
next prev parent reply other threads:[~2018-03-28 15:31 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-23 17:15 Alexandre Belloni
2018-02-23 17:15 ` [PATCH v3 1/6] ARM: at91: add TCB registers definitions Alexandre Belloni
2018-02-23 17:15 ` [PATCH v3 2/6] clocksource/drivers: Add a new driver for the Atmel ARM TC blocks Alexandre Belloni
2018-02-23 17:15 ` [PATCH v3 3/6] clocksource/drivers: atmel-pit: make option silent Alexandre Belloni
2018-02-23 17:15 ` [PATCH v3 4/6] ARM: at91: Implement clocksource selection Alexandre Belloni
2018-02-23 17:15 ` [PATCH v3 5/6] ARM: configs: at91: use new TCB timer driver Alexandre Belloni
2018-02-23 17:15 ` [PATCH v3 6/6] ARM: configs: at91: unselect PIT Alexandre Belloni
2018-03-22 15:33 ` [PATCH v3 0/6] clocksource: rework Atmel TCB timer driver Alexandre Belloni
2018-03-27 10:41 ` Alexander Dahl
2018-03-27 11:30 ` Daniel Lezcano
2018-03-28 10:29 ` Alexander Dahl
2018-03-28 13:03 ` Daniel Lezcano
2018-03-28 14:16 ` Alexandre Belloni
2018-03-28 14:36 ` Daniel Lezcano
2018-03-28 15:31 ` Alexandre Belloni [this message]
2018-03-28 15:50 ` Alexandre Belloni
2018-03-29 8:01 ` Alexander Dahl
2018-03-29 10:45 ` Alexandre Belloni
2018-03-29 11:31 ` Alexander Dahl
2018-03-29 11:42 ` Alexandre Belloni
2018-03-29 12:07 ` Daniel Lezcano
2018-03-29 13:02 ` Alexandre Belloni
2018-03-29 15:11 ` Alexander Dahl
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