From: Vignesh Raghavendra <vigneshr@ti.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Ashish Kumar <Ashish.Kumar@nxp.com>,
<linux-mtd@lists.infradead.org>, <linux-kernel@vger.kernel.org>,
John Garry <john.garry@huawei.com>
Subject: [PATCH 2/3] mtd: spi-nor: Add entries for mt25q variants
Date: Thu, 5 Dec 2019 12:29:34 +0530 [thread overview]
Message-ID: <20191205065935.5727-3-vigneshr@ti.com> (raw)
In-Reply-To: <20191205065935.5727-1-vigneshr@ti.com>
Add entries for mt25q*256a and mt25q*512a flashes. These are similar to
existing n25q variants but support stateless 4 byte addressing opcodes
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index 01efea022990..a5cb647378f0 100644
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -2456,8 +2456,17 @@ static const struct flash_info spi_nor_ids[] = {
{ "n25q064a", INFO(0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "mt25ql256a", INFO6(0x20ba19, 0x104400, 64 * 1024, 512,
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { "mt25qu256a", INFO6(0x20bb19, 0x104400, 64 * 1024, 512,
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q256ax1", INFO(0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) },
+ { "mt25ql512a", INFO6(0x20ba20, 0x104400, 64 * 1024, 1024,
+ SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
+ SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ "mt25qu512a", INFO6(0x20bb20, 0x104400, 64 * 1024, 1024,
SECT_4K | USE_FSR | SPI_NOR_DUAL_READ |
--
2.24.0
next prev parent reply other threads:[~2019-12-05 6:59 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-05 6:59 [PATCH 0/3] mtd: spi-nor: Update mt25q/n25q entries Vignesh Raghavendra
2019-12-05 6:59 ` [PATCH 1/3] mtd: spi-nor: Split mt25qu512a (n25q512a) entry into two Vignesh Raghavendra
2019-12-05 7:24 ` [EXT] " Ashish Kumar
2019-12-06 9:32 ` Vignesh Raghavendra
2019-12-05 6:59 ` Vignesh Raghavendra [this message]
2019-12-05 6:59 ` [PATCH 3/3] mtd: spi-nor: Add USE_FSR flag for n25q* entries Vignesh Raghavendra
2019-12-05 11:21 ` John Garry
2019-12-10 16:41 ` Tudor.Ambarus
2019-12-12 7:31 ` Vignesh Raghavendra
2019-12-24 9:05 ` [PATCH 0/3] mtd: spi-nor: Update mt25q/n25q entries Tudor.Ambarus
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