[PATCH] bus: ti-sysc: Fix missing reset delay handling

[PATCH] bus: ti-sysc: Fix missing reset delay handling

[Tony Lindgren]

We have dts property for "ti,sysc-delay-us", and we're using it, but the
wait after OCP softreset only happens if devices are probed in legacy mode.

Let's add a delay after writing the OCP softreset when specified.

Fixes: e0db94fe87da ("bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bits")
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 drivers/bus/ti-sysc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -1590,6 +1590,10 @@ static int sysc_reset(struct sysc *ddata)
 	sysc_val |= sysc_mask;
 	sysc_write(ddata, sysc_offset, sysc_val);
 
+	if (ddata->cfg.srst_udelay)
+		usleep_range(ddata->cfg.srst_udelay,
+			     ddata->cfg.srst_udelay * 2);
+
 	if (ddata->clk_enable_quirk)
 		ddata->clk_enable_quirk(ddata);
 
-- 
2.24.1

Re: [PATCH] bus: ti-sysc: Fix missing reset delay handling

[Keerthy]

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On 12/12/19 12:29 am, Tony Lindgren wrote:
> We have dts property for "ti,sysc-delay-us", and we're using it, but the
> wait after OCP softreset only happens if devices are probed in legacy mode.
> 
> Let's add a delay after writing the OCP softreset when specified.


Hi Tony,

Boot tested on DRA72 & DRA76.

Tested for RTC+DDR mode and DS0 mode on AM437x.
Tested for DS0 on am335x-evm & am335x-beagle-bone-black.

FWIW

Tested-by: Keerthy <j-keerthy@ti.com>

- Keerthy


> 
> Fixes: e0db94fe87da ("bus: ti-sysc: Make OCP reset work for sysstatus and sysconfig reset bits")
> Cc: Keerthy <j-keerthy@ti.com>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> ---
>  drivers/bus/ti-sysc.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
> --- a/drivers/bus/ti-sysc.c
> +++ b/drivers/bus/ti-sysc.c
> @@ -1590,6 +1590,10 @@ static int sysc_reset(struct sysc *ddata)
>  	sysc_val |= sysc_mask;
>  	sysc_write(ddata, sysc_offset, sysc_val);
>  
> +	if (ddata->cfg.srst_udelay)
> +		usleep_range(ddata->cfg.srst_udelay,
> +			     ddata->cfg.srst_udelay * 2);
> +
>  	if (ddata->clk_enable_quirk)
>  		ddata->clk_enable_quirk(ddata);
>  
> 

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