[V2] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC

[V2] x86/tsc: Unset TSC_KNOWN_FREQ and TSC_RELIABLE flags on Intel Bay Trail SoC

[Vipul Kumar]

From: Vipul Kumar <vipul_kumar@mentor.com>

'commit f3a02ecebed7 ("x86/tsc: Set TSC_KNOWN_FREQ and TSC_RELIABLE
flags on Intel Atom SoCs")', causing time drift for Bay trail SoC.
These flags are set for SoCs having cpuid_level 0x15 or more.
Bay trail is having cpuid_level 0xb.

So, unset both flags to make sure the clocksource calibration can
be done.

Signed-off-by: Vipul Kumar <vipul_kumar@mentor.com>
Cc: <stable@vger.kernel.org> # 4.14+
---
- Changes in v2:
- Added linux-stable along with kernel version in CC
---
 arch/x86/kernel/tsc_msr.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/tsc_msr.c b/arch/x86/kernel/tsc_msr.c
index e0cbe4f2af49..1ca27c28db98 100644
--- a/arch/x86/kernel/tsc_msr.c
+++ b/arch/x86/kernel/tsc_msr.c
@@ -112,6 +112,9 @@ unsigned long cpu_khz_from_msr(void)
 	lapic_timer_period = (freq * 1000) / HZ;
 #endif
 
+	if (boot_cpu_data.cpuid_level < 0x15)
+		return res;
+
 	/*
 	 * TSC frequency determined by MSR is always considered "known"
 	 * because it is reported by HW.
-- 
2.20.1