[PATCH v2 1/1] pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

[PATCH v2 1/1] pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

[Grace Kao]

According to Braswell NDA Specification Update (#557593),
concurrent read accesses may result in returning 0xffffffff and write
instructions may be dropped. We have an established format for the
commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in
byt_gpio_irq_handler")

Signed-off-by: Grace Kao <grace.kao@intel.com>
---
 drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 4c74fdde576d..1093a6105d40 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
 	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	unsigned long pending;
+	unsigned long flags;
 	u32 intr_line;
 
 	chained_irq_enter(chip, desc);
 
+	raw_spin_lock_irqsave(&chv_lock, flags);
 	pending = readl(pctrl->regs + CHV_INTSTAT);
+	raw_spin_unlock_irqrestore(&chv_lock, flags);
+
 	for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
 		unsigned int irq, offset;
 
-- 
2.17.1

Re: [PATCH v2 1/1] pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

[Brian Norris]

[Regarding subject: this says v2 -- where's v1?]

Hi,

On Thu, Apr 16, 2020 at 8:07 PM Grace Kao <grace.kao@intel.com> wrote:
>
> According to Braswell NDA Specification Update (#557593),
> concurrent read accesses may result in returning 0xffffffff and write
> instructions may be dropped. We have an established format for the
> commit references, i.e.
> cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in
> byt_gpio_irq_handler")
>

Might deserve a Fixes tag and Cc stable:

Fixes: 0bd50d719b00 pinctrl: cherryview: prevent concurrent access to
GPIO controllers
Cc: stable@vger.kernel.org>

> Signed-off-by: Grace Kao <grace.kao@intel.com>

Seems like you should at least give me the reporter credit, if not the
actual authorship, since I did in fact write this patch...

Reported-by: Brian Norris <briannorris@chromium.org>

And since I approve of my own patch:

Reviewed-by: Brian Norris <briannorris@chromium.org>

[PATCH v2 1/1] pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

[Grace Kao]

According to Braswell NDA Specification Update (#557593),
concurrent read accesses may result in returning 0xffffffff and write
instructions may be dropped. We have an established format for the
commit references, i.e.
cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in
byt_gpio_irq_handler")

Signed-off-by: Grace Kao <grace.kao@intel.com>
Reported-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
---
 drivers/pinctrl/intel/pinctrl-cherryview.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c
index 4c74fdde576d..1093a6105d40 100644
--- a/drivers/pinctrl/intel/pinctrl-cherryview.c
+++ b/drivers/pinctrl/intel/pinctrl-cherryview.c
@@ -1479,11 +1479,15 @@ static void chv_gpio_irq_handler(struct irq_desc *desc)
 	struct chv_pinctrl *pctrl = gpiochip_get_data(gc);
 	struct irq_chip *chip = irq_desc_get_chip(desc);
 	unsigned long pending;
+	unsigned long flags;
 	u32 intr_line;
 
 	chained_irq_enter(chip, desc);
 
+	raw_spin_lock_irqsave(&chv_lock, flags);
 	pending = readl(pctrl->regs + CHV_INTSTAT);
+	raw_spin_unlock_irqrestore(&chv_lock, flags);
+
 	for_each_set_bit(intr_line, &pending, pctrl->community->nirqs) {
 		unsigned int irq, offset;
 
-- 
2.17.1

Re: [PATCH v2 1/1] pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

[Mika Westerberg]

On Fri, Apr 17, 2020 at 12:11:54PM +0800, Grace Kao wrote:
> According to Braswell NDA Specification Update (#557593),
> concurrent read accesses may result in returning 0xffffffff and write
> instructions may be dropped. We have an established format for the
> commit references, i.e.
> cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in
> byt_gpio_irq_handler")
> 
> Signed-off-by: Grace Kao <grace.kao@intel.com>
> Reported-by: Brian Norris <briannorris@chromium.org>
> Reviewed-by: Brian Norris <briannorris@chromium.org>

Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Re: [PATCH v2 1/1] pinctrl: cherryview: Add missing spinlock usage in chv_gpio_irq_handler

[Andy Shevchenko]

On Fri, Apr 17, 2020 at 12:08 PM Mika Westerberg
<mika.westerberg@linux.intel.com> wrote:
>
> On Fri, Apr 17, 2020 at 12:11:54PM +0800, Grace Kao wrote:
> > According to Braswell NDA Specification Update (#557593),
> > concurrent read accesses may result in returning 0xffffffff and write
> > instructions may be dropped. We have an established format for the
> > commit references, i.e.
> > cdca06e4e859 ("pinctrl: baytrail: Add missing spinlock usage in
> > byt_gpio_irq_handler")
> >
> > Signed-off-by: Grace Kao <grace.kao@intel.com>
> > Reported-by: Brian Norris <briannorris@chromium.org>
> > Reviewed-by: Brian Norris <briannorris@chromium.org>
>
> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>

Applied for fixes, thanks!

-- 
With Best Regards,
Andy Shevchenko