mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
* [PATCH v2] drm/arm: fixes pixel clock enabled with wrong format
@ 2020-04-24  6:35 Bernard Zhao
  2020-04-24 11:00 ` Emil Velikov
  2020-04-24 11:09 ` Liviu Dudau
  0 siblings, 2 replies; 3+ messages in thread
From: Bernard Zhao @ 2020-04-24  6:35 UTC (permalink / raw)
  To: Liviu Dudau, Brian Starkey, David Airlie, Daniel Vetter,
	dri-devel, linux-kernel
  Cc: opensource.kernel, Bernard Zhao

The pixel clock is still enabled when the format is wrong.
no error branch handle, and also some register is not set
in this case, e.g: HDLCD_REG_<color>_SELECT. Maybe we
should disable this clock and throw an warn message when
this happened.
With this change, the code maybe a bit more readable.

Signed-off-by: Bernard Zhao <bernard@vivo.com>

Changes since V1:
*add format error handle, if format is not correct, throw
an warning message and disable this clock.

Link for V1:
*https://lore.kernel.org/patchwork/patch/1228501/
---
 drivers/gpu/drm/arm/hdlcd_crtc.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
index af67fefed38d..f3945dee2b7d 100644
--- a/drivers/gpu/drm/arm/hdlcd_crtc.c
+++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
@@ -96,7 +96,7 @@ static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
 	}
 
 	if (WARN_ON(!format))
-		return 0;
+		return -EINVAL;
 
 	/* HDLCD uses 'bytes per pixel', zero means 1 byte */
 	btpp = (format->bits_per_pixel + 7) / 8;
@@ -125,7 +125,7 @@ static int hdlcd_set_pxl_fmt(struct drm_crtc *crtc)
 	return 0;
 }
 
-static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
+static int hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
 {
 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 	struct drm_display_mode *m = &crtc->state->adjusted_mode;
@@ -162,9 +162,10 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
 
 	err = hdlcd_set_pxl_fmt(crtc);
 	if (err)
-		return;
+		return err;
 
 	clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
+	return 0;
 }
 
 static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
@@ -173,7 +174,11 @@ static void hdlcd_crtc_atomic_enable(struct drm_crtc *crtc,
 	struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
 
 	clk_prepare_enable(hdlcd->clk);
-	hdlcd_crtc_mode_set_nofb(crtc);
+	if (hdlcd_crtc_mode_set_nofb(crtc)) {
+		DRM_DEBUG_KMS("Invalid format, pixel clock enable failed!\n");
+		clk_disable_unprepare(hdlcd->clk);
+		return;
+	}
 	hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
 	drm_crtc_vblank_on(crtc);
 }
-- 
2.26.2


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2020-04-24 11:09 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-24  6:35 [PATCH v2] drm/arm: fixes pixel clock enabled with wrong format Bernard Zhao
2020-04-24 11:00 ` Emil Velikov
2020-04-24 11:09 ` Liviu Dudau

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®