From: Mark Brown <broonie@kernel.org>
To: Dan Murphy <dmurphy@ti.com>
Cc: lgirdwood@gmail.com, perex@perex.cz, tiwai@suse.com,
alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ASoC: tlv320adcx140: Add controls for PDM clk and edge
Date: Wed, 13 May 2020 16:32:43 +0100 [thread overview]
Message-ID: <20200513153243.GO4803@sirena.org.uk> (raw)
In-Reply-To: <20200513144746.14337-1-dmurphy@ti.com>
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On Wed, May 13, 2020 at 09:47:46AM -0500, Dan Murphy wrote:
> +static const char * const pdmclk_text[] = {
> + "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
> +};
> +
> +static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
> + pdmclk_text);
> +
> +static const struct snd_kcontrol_new pdmclk_div_controls[] = {
> + SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
> +};
> +
> +static const char * const pdm_edge_text[] = {
> + "Negative", "Positive"
> +};
Are these (especially the clock and polarity) things that are going to
vary at runtime? I'd have expected these to come from the hardware
rather than being something that could usefully change.
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next prev parent reply other threads:[~2020-05-13 15:32 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 14:47 Dan Murphy
2020-05-13 15:32 ` Mark Brown [this message]
2020-05-13 17:16 ` Dan Murphy
2020-05-13 17:32 ` Mark Brown
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