From: Leo Yan <leo.yan@linaro.org>
To: Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@redhat.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Mark Rutland <mark.rutland@arm.com>,
Namhyung Kim <namhyung@kernel.org>,
"Naveen N. Rao" <naveen.n.rao@linux.vnet.ibm.com>,
Ian Rogers <irogers@google.com>,
Kemeng Shi <shikemeng@huawei.com>,
James Clark <james.clark@arm.com>, Wei Li <liwei391@huawei.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Al Grant <Al.Grant@arm.com>,
linux-kernel@vger.kernel.org,
Mathieu Poirier <mathieu.poirier@linaro.org>,
Mike Leach <mike.leach@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Subject: [PATCH RESEND v1 11/11] perf arm-spe: Set sample's data source field
Date: Thu, 6 Aug 2020 11:07:27 +0800 [thread overview]
Message-ID: <20200806030727.30267-12-leo.yan@linaro.org> (raw)
In-Reply-To: <20200806030727.30267-1-leo.yan@linaro.org>
The sample structure contains the field 'data_src' which is used to
tell the detailed info for data operations, e.g. this field indicates
the data operation is loading or storing, on which cache level, it's
snooping or remote accessing, etc. At the end, the 'data_src' will be
parsed by perf memory tool to display human readable strings.
This patch is to fill the 'data_src' field in the synthesized samples
base on different types. Now support types for Level 1 dcache miss,
Level 1 dcache hit, Last level cache miss, Last level cache access,
TLB miss, TLB hit, remote access for other socket.
Note, current perf tool can display statistics for L1/L2/L3 caches but
it doesn't support the 'last level cache'. To fit into current
implementation, 'data_src' field uses L3 cache for last level cache.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/util/arm-spe.c | 87 +++++++++++++++++++++++++++++++++++----
1 file changed, 79 insertions(+), 8 deletions(-)
diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c
index 74308a72b000..3114f059fc2f 100644
--- a/tools/perf/util/arm-spe.c
+++ b/tools/perf/util/arm-spe.c
@@ -259,7 +259,7 @@ arm_spe_deliver_synth_event(struct arm_spe *spe,
}
static int arm_spe__synth_mem_sample(struct arm_spe_queue *speq,
- u64 spe_events_id)
+ u64 spe_events_id, u64 data_src)
{
struct arm_spe *spe = speq->spe;
struct arm_spe_record *record = &speq->decoder->record;
@@ -272,6 +272,7 @@ static int arm_spe__synth_mem_sample(struct arm_spe_queue *speq,
sample.stream_id = spe_events_id;
sample.addr = record->addr;
sample.phys_addr = record->phys_addr;
+ sample.data_src = data_src;
return arm_spe_deliver_synth_event(spe, speq, event, &sample);
}
@@ -293,21 +294,74 @@ static int arm_spe__synth_branch_sample(struct arm_spe_queue *speq,
return arm_spe_deliver_synth_event(spe, speq, event, &sample);
}
+static u64 arm_spe__synth_data_source(const struct arm_spe_record *record,
+ int type)
+{
+ union perf_mem_data_src data_src = { 0 };
+
+ if (record->op == ARM_SPE_LD)
+ data_src.mem_op = PERF_MEM_OP_LOAD;
+ else
+ data_src.mem_op = PERF_MEM_OP_STORE;
+
+ switch (type) {
+ case ARM_SPE_L1D_MISS:
+ data_src.mem_lvl_num = PERF_MEM_LVLNUM_L1;
+ data_src.mem_lvl = PERF_MEM_LVL_MISS | PERF_MEM_LVL_L1;
+ break;
+ case ARM_SPE_L1D_ACCESS:
+ data_src.mem_lvl_num = PERF_MEM_LVLNUM_L1;
+ data_src.mem_lvl = PERF_MEM_LVL_HIT | PERF_MEM_LVL_L1;
+ break;
+ case ARM_SPE_LLC_MISS:
+ data_src.mem_lvl_num = PERF_MEM_LVLNUM_L3;
+ data_src.mem_lvl = PERF_MEM_LVL_MISS | PERF_MEM_LVL_L3;
+ break;
+ case ARM_SPE_LLC_ACCESS:
+ data_src.mem_lvl_num = PERF_MEM_LVLNUM_L3;
+ data_src.mem_lvl = PERF_MEM_LVL_HIT | PERF_MEM_LVL_L3;
+ break;
+ case ARM_SPE_TLB_MISS:
+ data_src.mem_dtlb = PERF_MEM_TLB_WK | PERF_MEM_TLB_MISS;
+ break;
+ case ARM_SPE_TLB_ACCESS:
+ data_src.mem_dtlb = PERF_MEM_TLB_WK | PERF_MEM_TLB_HIT;
+ break;
+ case ARM_SPE_REMOTE_ACCESS:
+ data_src.mem_lvl_num = PERF_MEM_LVLNUM_ANY_CACHE;
+ data_src.mem_lvl = PERF_MEM_LVL_HIT | PERF_MEM_LVL_REM_CCE1;
+ break;
+ default:
+ break;
+ }
+
+ return data_src.val;
+}
+
static int arm_spe_sample(struct arm_spe_queue *speq)
{
const struct arm_spe_record *record = &speq->decoder->record;
struct arm_spe *spe = speq->spe;
+ u64 data_src;
int err;
if (spe->sample_flc) {
if (record->type & ARM_SPE_L1D_MISS) {
- err = arm_spe__synth_mem_sample(speq, spe->l1d_miss_id);
+ data_src = arm_spe__synth_data_source(record,
+ ARM_SPE_L1D_MISS);
+
+ err = arm_spe__synth_mem_sample(speq, spe->l1d_miss_id,
+ data_src);
if (err)
return err;
}
if (record->type & ARM_SPE_L1D_ACCESS) {
- err = arm_spe__synth_mem_sample(speq, spe->l1d_access_id);
+ data_src = arm_spe__synth_data_source(record,
+ ARM_SPE_L1D_ACCESS);
+
+ err = arm_spe__synth_mem_sample(speq, spe->l1d_access_id,
+ data_src);
if (err)
return err;
}
@@ -315,13 +369,21 @@ static int arm_spe_sample(struct arm_spe_queue *speq)
if (spe->sample_llc) {
if (record->type & ARM_SPE_LLC_MISS) {
- err = arm_spe__synth_mem_sample(speq, spe->llc_miss_id);
+ data_src = arm_spe__synth_data_source(record,
+ ARM_SPE_LLC_MISS);
+
+ err = arm_spe__synth_mem_sample(speq, spe->llc_miss_id,
+ data_src);
if (err)
return err;
}
if (record->type & ARM_SPE_LLC_ACCESS) {
- err = arm_spe__synth_mem_sample(speq, spe->llc_access_id);
+ data_src = arm_spe__synth_data_source(record,
+ ARM_SPE_LLC_ACCESS);
+
+ err = arm_spe__synth_mem_sample(speq, spe->llc_access_id,
+ data_src);
if (err)
return err;
}
@@ -329,13 +391,19 @@ static int arm_spe_sample(struct arm_spe_queue *speq)
if (spe->sample_tlb) {
if (record->type & ARM_SPE_TLB_MISS) {
- err = arm_spe__synth_mem_sample(speq, spe->tlb_miss_id);
+ data_src = arm_spe__synth_data_source(record,
+ ARM_SPE_TLB_MISS);
+ err = arm_spe__synth_mem_sample(speq, spe->tlb_miss_id,
+ data_src);
if (err)
return err;
}
if (record->type & ARM_SPE_TLB_ACCESS) {
- err = arm_spe__synth_mem_sample(speq, spe->tlb_access_id);
+ data_src = arm_spe__synth_data_source(record,
+ ARM_SPE_TLB_ACCESS);
+ err = arm_spe__synth_mem_sample(speq, spe->tlb_access_id,
+ data_src);
if (err)
return err;
}
@@ -349,7 +417,10 @@ static int arm_spe_sample(struct arm_spe_queue *speq)
if (spe->sample_remote_access &&
(record->type & ARM_SPE_REMOTE_ACCESS)) {
- err = arm_spe__synth_mem_sample(speq, spe->remote_access_id);
+ data_src = arm_spe__synth_data_source(record,
+ ARM_SPE_REMOTE_ACCESS);
+ err = arm_spe__synth_mem_sample(speq, spe->remote_access_id,
+ data_src);
if (err)
return err;
}
--
2.17.1
next prev parent reply other threads:[~2020-08-06 3:08 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-06 3:07 [PATCH RESEND v1 00/11] perf mem: Support AUX trace and Arm SPE Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 01/11] perf mem: Search event name with more flexible path Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 02/11] perf mem: Introduce weak function perf_mem_events__ptr() Leo Yan
2020-08-28 15:40 ` James Clark
2020-08-31 2:52 ` Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 03/11] perf mem: Support new memory event PERF_MEM_EVENTS__LOAD_STORE Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 04/11] perf mem: Only initialize memory event for recording Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 05/11] perf mem: Support AUX trace Leo Yan
2020-09-01 15:52 ` James Clark
2020-09-03 9:07 ` Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 06/11] perf mem: Support Arm SPE events Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 07/11] perf arm-spe: Enable attribution PERF_SAMPLE_DATA_SRC Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 08/11] perf arm-spe: Save memory addresses in packet Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 09/11] perf arm-spe: Store operation types " Leo Yan
2020-08-06 3:07 ` [PATCH RESEND v1 10/11] perf arm-spe: Fill address info for memory samples Leo Yan
2020-08-06 3:07 ` Leo Yan [this message]
2020-09-01 16:36 ` [PATCH RESEND v1 00/11] perf mem: Support AUX trace and Arm SPE James Clark
2020-09-03 9:13 ` Leo Yan
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