[PATCH 0/3] r8a7742-iwg21m enable RTC and NOR flash

[PATCH 0/3] r8a7742-iwg21m enable RTC and NOR flash

[Lad Prabhakar]

Hi All,

This series enables RTC and SPI NOR found on r8a7742-iwg21m
SoM.

Cheers,
Prabhakar

Lad Prabhakar (3):
  ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically
  ARM: dts: r8a7742-iwg21m: Add RTC support
  ARM: dts: r8a7742-iwg21m: Add SPI NOR support

 arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 62 +++++++++++++++++++++++++--
 1 file changed, 58 insertions(+), 4 deletions(-)

-- 
2.17.1

[PATCH 1/3] ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically

[Lad Prabhakar]

Sort the DT nodes alphabetically so that its easier to maintain.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
index 85aff429d408..6e8df79bea94 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -35,13 +35,6 @@
 	clock-frequency = <20000000>;
 };
 
-&pfc {
-	mmc1_pins: mmc1 {
-		groups = "mmc1_data4", "mmc1_ctrl";
-		function = "mmc1";
-	};
-};
-
 &mmcif1 {
 	pinctrl-0 = <&mmc1_pins>;
 	pinctrl-names = "default";
@@ -51,3 +44,10 @@
 	non-removable;
 	status = "okay";
 };
+
+&pfc {
+	mmc1_pins: mmc1 {
+		groups = "mmc1_data4", "mmc1_ctrl";
+		function = "mmc1";
+	};
+};
-- 
2.17.1

Re: [PATCH 1/3] ARM: dts: r8a7742-iwg21m: Sort the nodes alphabetically

[Geert Uytterhoeven]

On Sun, Aug 16, 2020 at 9:33 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Sort the DT nodes alphabetically so that its easier to maintain.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 2/3] ARM: dts: r8a7742-iwg21m: Add RTC support

[Lad Prabhakar]

Enable BQ32000 RTC which is connected to I2C0 on the iWave RainboW-G21M-q7
SOM.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
index 6e8df79bea94..0f26807f92b8 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -35,6 +35,21 @@
 	clock-frequency = <20000000>;
 };
 
+&i2c0 {
+	pinctrl-0 = <&i2c0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+	clock-frequency = <400000>;
+
+	rtc@68 {
+		compatible = "ti,bq32000";
+		reg = <0x68>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+	};
+};
+
 &mmcif1 {
 	pinctrl-0 = <&mmc1_pins>;
 	pinctrl-names = "default";
@@ -46,6 +61,11 @@
 };
 
 &pfc {
+	i2c0_pins: i2c0 {
+		groups = "i2c0";
+		function = "i2c0";
+	};
+
 	mmc1_pins: mmc1 {
 		groups = "mmc1_data4", "mmc1_ctrl";
 		function = "mmc1";
-- 
2.17.1

Re: [PATCH 2/3] ARM: dts: r8a7742-iwg21m: Add RTC support

[Geert Uytterhoeven]

On Sun, Aug 16, 2020 at 9:33 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Enable BQ32000 RTC which is connected to I2C0 on the iWave RainboW-G21M-q7
> SOM.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.10.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 3/3] ARM: dts: r8a7742-iwg21m: Add SPI NOR support

[Lad Prabhakar]

Add support for the SPI NOR device used to boot up the system
to the System on Module DT.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
---
 arch/arm/boot/dts/r8a7742-iwg21m.dtsi | 34 +++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)

diff --git a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
index 0f26807f92b8..db8301331d31 100644
--- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
+++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
@@ -35,6 +35,16 @@
 	clock-frequency = <20000000>;
 };
 
+&gpio0 {
+	/* GP0_18 set low to select QSPI. Doing so will disable VIN2 */
+	qspi_en {
+		gpio-hog;
+		gpios = <18 GPIO_ACTIVE_HIGH>;
+		output-low;
+		line-name = "QSPI_EN";
+	};
+};
+
 &i2c0 {
 	pinctrl-0 = <&i2c0_pins>;
 	pinctrl-names = "default";
@@ -70,4 +80,28 @@
 		groups = "mmc1_data4", "mmc1_ctrl";
 		function = "mmc1";
 	};
+
+	qspi_pins: qspi {
+		groups = "qspi_ctrl", "qspi_data2";
+		function = "qspi";
+	};
+};
+
+&qspi {
+	pinctrl-0 = <&qspi_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	/* WARNING - This device contains the bootloader. Handle with care. */
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "sst,sst25vf016b", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		spi-cpol;
+		spi-cpha;
+	};
 };
-- 
2.17.1

Re: [PATCH 3/3] ARM: dts: r8a7742-iwg21m: Add SPI NOR support

[kernel test robot]

[-- Attachment #1: Type: text/plain, Size: 1338 bytes --]

Hi Lad,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on renesas-devel/next]
[also build test ERROR on v5.8 next-20200814]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Lad-Prabhakar/r8a7742-iwg21m-enable-RTC-and-NOR-flash/20200817-033555
base:   https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> Error: arch/arm/boot/dts/r8a7742-iwg21m.dtsi:90.1-6 Label or path qspi not found
>> FATAL ERROR: Syntax error parsing input tree

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 52664 bytes --]

Re: [PATCH 3/3] ARM: dts: r8a7742-iwg21m: Add SPI NOR support

[Geert Uytterhoeven]

Hi Prabhakar,

On Sun, Aug 16, 2020 at 9:33 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add support for the SPI NOR device used to boot up the system
> to the System on Module DT.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>

Thanks for your patch!

> --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
> +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi

> @@ -70,4 +80,28 @@
>                 groups = "mmc1_data4", "mmc1_ctrl";
>                 function = "mmc1";
>         };
> +
> +       qspi_pins: qspi {
> +               groups = "qspi_ctrl", "qspi_data2";
> +               function = "qspi";
> +       };
> +};
> +
> +&qspi {
> +       pinctrl-0 = <&qspi_pins>;
> +       pinctrl-names = "default";
> +
> +       status = "okay";
> +
> +       /* WARNING - This device contains the bootloader. Handle with care. */
> +       flash: flash@0 {
> +               #address-cells = <1>;
> +               #size-cells = <1>;

#{address,size}-cells are not needed, unless you list legacy partitions
(i.e. partitions not contained in a "partitions" container).

> +               compatible = "sst,sst25vf016b", "jedec,spi-nor";
> +               reg = <0>;
> +               spi-max-frequency = <50000000>;
> +               m25p,fast-read;
> +               spi-cpol;
> +               spi-cpha;

Perhaps you want to add the partition layout, too?

> +       };
>  };

With the above fixed/clarified:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/3] ARM: dts: r8a7742-iwg21m: Add SPI NOR support

[Lad, Prabhakar]

Hi Geert,

Thank you for the review.

On Fri, Aug 21, 2020 at 2:33 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Sun, Aug 16, 2020 at 9:33 PM Lad Prabhakar
> <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > Add support for the SPI NOR device used to boot up the system
> > to the System on Module DT.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
> > +++ b/arch/arm/boot/dts/r8a7742-iwg21m.dtsi
>
> > @@ -70,4 +80,28 @@
> >                 groups = "mmc1_data4", "mmc1_ctrl";
> >                 function = "mmc1";
> >         };
> > +
> > +       qspi_pins: qspi {
> > +               groups = "qspi_ctrl", "qspi_data2";
> > +               function = "qspi";
> > +       };
> > +};
> > +
> > +&qspi {
> > +       pinctrl-0 = <&qspi_pins>;
> > +       pinctrl-names = "default";
> > +
> > +       status = "okay";
> > +
> > +       /* WARNING - This device contains the bootloader. Handle with care. */
> > +       flash: flash@0 {
> > +               #address-cells = <1>;
> > +               #size-cells = <1>;
>
> #{address,size}-cells are not needed, unless you list legacy partitions
> (i.e. partitions not contained in a "partitions" container).
>
Agreed will drop it.

> > +               compatible = "sst,sst25vf016b", "jedec,spi-nor";
> > +               reg = <0>;
> > +               spi-max-frequency = <50000000>;
> > +               m25p,fast-read;
> > +               spi-cpol;
> > +               spi-cpha;
>
> Perhaps you want to add the partition layout, too?
>
will do.

> > +       };
> >  };
>
> With the above fixed/clarified:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
Thank you. I shall post this lone patch fixing the above.

Cheers,
Prabhakar

> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds