* [PATCHv2] arm64: dts: qcom: sc7180: Fix the LLCC base register size
@ 2020-08-18 14:55 Sai Prakash Ranjan
2020-08-18 14:57 ` Doug Anderson
0 siblings, 1 reply; 2+ messages in thread
From: Sai Prakash Ranjan @ 2020-08-18 14:55 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Douglas Anderson, Stephen Boyd
Cc: devicetree, linux-arm-kernel, linux-arm-msm, linux-kernel,
Sai Prakash Ranjan
There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
the size and fix copy paste mistake carried over from SDM845.
Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
Changes in v2:
* Edit commit msg to remove confusing references (Doug).
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index d46b3833e52f..e875f6c3b663 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2618,7 +2618,7 @@ dc_noc: interconnect@9160000 {
system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc";
- reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
+ reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCHv2] arm64: dts: qcom: sc7180: Fix the LLCC base register size
2020-08-18 14:55 [PATCHv2] arm64: dts: qcom: sc7180: Fix the LLCC base register size Sai Prakash Ranjan
@ 2020-08-18 14:57 ` Doug Anderson
0 siblings, 0 replies; 2+ messages in thread
From: Doug Anderson @ 2020-08-18 14:57 UTC (permalink / raw)
To: Sai Prakash Ranjan
Cc: Andy Gross, Bjorn Andersson, Stephen Boyd,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux ARM, linux-arm-msm, LKML
Hi,
On Tue, Aug 18, 2020 at 7:55 AM Sai Prakash Ranjan
<saiprakash.ranjan@codeaurora.org> wrote:
>
> There is one LLCC logical bank(LLCC0) on SC7180 SoC and the
> size of the LLCC0 base is 0x50000(320KB) not 2MB, so correct
> the size and fix copy paste mistake carried over from SDM845.
>
> Fixes: 7cee5c742899 ("arm64: dts: qcom: sc7180: Fix node order")
> Fixes: c831fa299996 ("arm64: dts: qcom: sc7180: Add Last level cache controller node")
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>
> Changes in v2:
> * Edit commit msg to remove confusing references (Doug).
>
> ---
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
I can't validate against any datasheets, but it does what it says and
seems sane.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
^ permalink raw reply [flat|nested] 2+ messages in thread
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