From: Russ Weight <russell.h.weight@intel.com>
To: mdf@kernel.org, lee.jones@linaro.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com,
hao.wu@intel.com, matthew.gerlach@intel.com,
Russ Weight <russell.h.weight@intel.com>
Subject: [PATCH v2 3/6] fpga: m10bmc-sec: expose max10 flash update counts
Date: Fri, 2 Oct 2020 18:24:09 -0700 [thread overview]
Message-ID: <20201003012412.16831-4-russell.h.weight@intel.com> (raw)
In-Reply-To: <20201003012412.16831-1-russell.h.weight@intel.com>
Extend the MAX10 BMC Security Engine driver to provide a
handler to expose the flash update count for the FPGA user
image in sysfs.
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
---
v2:
- Renamed get_qspi_flash_count() to m10bmc_user_flash_count()
- Minor code cleanup per review comments
- Added m10bmc_ prefix to functions in m10bmc_iops structure
---
drivers/fpga/intel-m10-bmc-secure.c | 31 +++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c
index df8ebda9a9cb..da61cfda3c50 100644
--- a/drivers/fpga/intel-m10-bmc-secure.c
+++ b/drivers/fpga/intel-m10-bmc-secure.c
@@ -11,6 +11,7 @@
#include <linux/mfd/intel-m10-bmc.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/slab.h>
#include <linux/vmalloc.h>
struct m10bmc_sec {
@@ -105,7 +106,37 @@ static int m10bmc_pr_root_entry_hash(struct ifpga_sec_mgr *imgr,
return m10bmc_root_entry_hash(imgr, PR_REH_ADDR, hash, size);
}
+#define FLASH_COUNT_SIZE 4096 /* count stored in inverted bit vector */
+
+static int m10bmc_user_flash_count(struct ifpga_sec_mgr *imgr)
+{
+ struct m10bmc_sec *sec = imgr->priv;
+ unsigned int stride = regmap_get_reg_stride(sec->m10bmc->regmap);
+ unsigned int num_bits = FLASH_COUNT_SIZE * 8;
+ u8 *flash_buf;
+ int ret;
+
+ flash_buf = kmalloc(FLASH_COUNT_SIZE, GFP_KERNEL);
+ if (!flash_buf)
+ return -ENOMEM;
+
+ ret = m10bmc_raw_bulk_read(sec->m10bmc, USER_FLASH_COUNT, flash_buf,
+ FLASH_COUNT_SIZE / stride);
+ if (ret) {
+ dev_err(sec->dev, "%s failed to read %d\n", __func__, ret);
+ goto exit_free;
+ }
+
+ ret = num_bits - bitmap_weight((unsigned long *)flash_buf, num_bits);
+
+exit_free:
+ kfree(flash_buf);
+
+ return ret;
+}
+
static const struct ifpga_sec_mgr_ops m10bmc_iops = {
+ .user_flash_count = m10bmc_user_flash_count,
.bmc_root_entry_hash = m10bmc_bmc_root_entry_hash,
.sr_root_entry_hash = m10bmc_sr_root_entry_hash,
.pr_root_entry_hash = m10bmc_pr_root_entry_hash,
--
2.17.1
next prev parent reply other threads:[~2020-10-03 1:24 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-03 1:24 [PATCH v2 0/6] Intel MAX10 BMC Security Engine Driver Russ Weight
2020-10-03 1:24 ` [PATCH v2 1/6] mfd: intel-m10-bmc: support for MAX10 BMC Security Engine Russ Weight
2020-10-06 16:34 ` Tom Rix
2020-10-08 0:52 ` Russ Weight
2020-10-08 23:03 ` Russ Weight
2020-10-09 20:04 ` Tom Rix
2020-10-07 7:00 ` Lee Jones
2020-10-08 0:49 ` Russ Weight
2020-10-08 7:23 ` Lee Jones
2020-10-03 1:24 ` [PATCH v2 2/6] fpga: m10bmc-sec: create max10 bmc security engine Russ Weight
2020-10-03 3:15 ` Randy Dunlap
2020-10-04 18:01 ` Russ Weight
2020-10-04 18:07 ` Randy Dunlap
2020-10-06 17:31 ` Tom Rix
2020-10-08 21:12 ` Russ Weight
2020-10-03 1:24 ` Russ Weight [this message]
2020-10-06 17:35 ` [PATCH v2 3/6] fpga: m10bmc-sec: expose max10 flash update counts Tom Rix
2020-10-03 1:24 ` [PATCH v2 4/6] fpga: m10bmc-sec: expose max10 canceled keys in sysfs Russ Weight
2020-10-06 17:41 ` Tom Rix
2020-10-03 1:24 ` [PATCH v2 5/6] fpga: m10bmc-sec: add max10 secure update functions Russ Weight
2020-10-06 19:08 ` Tom Rix
2020-10-08 23:06 ` Russ Weight
2020-10-09 20:15 ` Tom Rix
2020-10-03 1:24 ` [PATCH v2 6/6] fpga: m10bmc-sec: add max10 get_hw_errinfo callback func Russ Weight
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