From: Russ Weight <russell.h.weight@intel.com>
To: mdf@kernel.org, lee.jones@linaro.org, linux-fpga@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: trix@redhat.com, lgoncalv@redhat.com, yilun.xu@intel.com,
hao.wu@intel.com, matthew.gerlach@intel.com,
Russ Weight <russell.h.weight@intel.com>
Subject: [PATCH v2 6/6] fpga: m10bmc-sec: add max10 get_hw_errinfo callback func
Date: Fri, 2 Oct 2020 18:24:12 -0700 [thread overview]
Message-ID: <20201003012412.16831-7-russell.h.weight@intel.com> (raw)
In-Reply-To: <20201003012412.16831-1-russell.h.weight@intel.com>
Extend the MAX10 BMC Security Engine driver to include
a function that returns 64 bits of additional HW specific
data for errors that require additional information.
This callback function enables the hw_errinfo sysfs
node in the Intel Security Manager class driver.
Signed-off-by: Russ Weight <russell.h.weight@intel.com>
---
v2:
- Implemented HW_ERRINFO_POISON for m10bmc_sec_hw_errinfo() to
ensure that corresponding bits are set to 1 if we are unable
to read the doorbell or auth_result registers.
- Added m10bmc_ prefix to functions in m10bmc_iops structure
---
drivers/fpga/intel-m10-bmc-secure.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c
index a9617c5b3845..9edc39439c97 100644
--- a/drivers/fpga/intel-m10-bmc-secure.c
+++ b/drivers/fpga/intel-m10-bmc-secure.c
@@ -495,6 +495,30 @@ static enum ifpga_sec_err m10bmc_sec_cancel(struct ifpga_sec_mgr *imgr)
return ret ? IFPGA_SEC_ERR_RW_ERROR : IFPGA_SEC_ERR_NONE;
}
+#define HW_ERRINFO_POISON GENMASK(31, 0)
+static u64 m10bmc_sec_hw_errinfo(struct ifpga_sec_mgr *imgr)
+{
+ struct m10bmc_sec *sec = imgr->priv;
+ u32 doorbell, auth_result;
+
+ switch (imgr->err_code) {
+ case IFPGA_SEC_ERR_HW_ERROR:
+ case IFPGA_SEC_ERR_TIMEOUT:
+ case IFPGA_SEC_ERR_BUSY:
+ case IFPGA_SEC_ERR_WEAROUT:
+ if (m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell))
+ doorbell = HW_ERRINFO_POISON;
+
+ if (m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT,
+ &auth_result))
+ auth_result = HW_ERRINFO_POISON;
+
+ return (u64)doorbell << 32 | (u64)auth_result;
+ default:
+ return 0;
+ }
+}
+
static const struct ifpga_sec_mgr_ops m10bmc_iops = {
.user_flash_count = m10bmc_user_flash_count,
.bmc_root_entry_hash = m10bmc_bmc_root_entry_hash,
@@ -513,6 +537,7 @@ static const struct ifpga_sec_mgr_ops m10bmc_iops = {
.write_blk = m10bmc_sec_write_blk,
.poll_complete = m10bmc_sec_poll_complete,
.cancel = m10bmc_sec_cancel,
+ .get_hw_errinfo = m10bmc_sec_hw_errinfo,
};
static int m10bmc_secure_probe(struct platform_device *pdev)
--
2.17.1
prev parent reply other threads:[~2020-10-03 1:24 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-03 1:24 [PATCH v2 0/6] Intel MAX10 BMC Security Engine Driver Russ Weight
2020-10-03 1:24 ` [PATCH v2 1/6] mfd: intel-m10-bmc: support for MAX10 BMC Security Engine Russ Weight
2020-10-06 16:34 ` Tom Rix
2020-10-08 0:52 ` Russ Weight
2020-10-08 23:03 ` Russ Weight
2020-10-09 20:04 ` Tom Rix
2020-10-07 7:00 ` Lee Jones
2020-10-08 0:49 ` Russ Weight
2020-10-08 7:23 ` Lee Jones
2020-10-03 1:24 ` [PATCH v2 2/6] fpga: m10bmc-sec: create max10 bmc security engine Russ Weight
2020-10-03 3:15 ` Randy Dunlap
2020-10-04 18:01 ` Russ Weight
2020-10-04 18:07 ` Randy Dunlap
2020-10-06 17:31 ` Tom Rix
2020-10-08 21:12 ` Russ Weight
2020-10-03 1:24 ` [PATCH v2 3/6] fpga: m10bmc-sec: expose max10 flash update counts Russ Weight
2020-10-06 17:35 ` Tom Rix
2020-10-03 1:24 ` [PATCH v2 4/6] fpga: m10bmc-sec: expose max10 canceled keys in sysfs Russ Weight
2020-10-06 17:41 ` Tom Rix
2020-10-03 1:24 ` [PATCH v2 5/6] fpga: m10bmc-sec: add max10 secure update functions Russ Weight
2020-10-06 19:08 ` Tom Rix
2020-10-08 23:06 ` Russ Weight
2020-10-09 20:15 ` Tom Rix
2020-10-03 1:24 ` Russ Weight [this message]
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