* [PATCH v2 1/4] pinctrl: amd: fix incorrect way to disable debounce filter
[not found] <20201104230703.21466-1-coiby.xu@gmail.com>
@ 2020-11-04 23:07 ` Coiby Xu
2020-11-04 23:07 ` [PATCH v2 2/4] pinctrl: amd: use higher precision for 512 RtcClk Coiby Xu
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Coiby Xu @ 2020-11-04 23:07 UTC (permalink / raw)
To: Linus Walleij
Cc: Andy Shevchenko, Hans de Goede, open list:PIN CONTROL SUBSYSTEM,
open list
The correct way to disable debounce filter is to clear bit 5 and 6
of the register.
Cc: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/linux-gpio/df2c008b-e7b5-4fdd-42ea-4d1c62b52139@redhat.com/
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
---
drivers/pinctrl/pinctrl-amd.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 9a760f5cd7ed..d6b2b4bd337c 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -166,14 +166,14 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg |= BIT(DB_TMR_LARGE_OFF);
} else {
- pin_reg &= ~DB_CNTRl_MASK;
+ pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
ret = -EINVAL;
}
} else {
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
pin_reg &= ~DB_TMR_OUT_MASK;
- pin_reg &= ~DB_CNTRl_MASK;
+ pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
}
writel(pin_reg, gpio_dev->base + offset * 4);
raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
--
2.28.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 2/4] pinctrl: amd: use higher precision for 512 RtcClk
[not found] <20201104230703.21466-1-coiby.xu@gmail.com>
2020-11-04 23:07 ` [PATCH v2 1/4] pinctrl: amd: fix incorrect way to disable debounce filter Coiby Xu
@ 2020-11-04 23:07 ` Coiby Xu
2020-11-05 11:13 ` Andy Shevchenko
2020-11-04 23:07 ` [PATCH v2 3/4] pinctrl: amd: print debounce filter info in debugfs Coiby Xu
2020-11-04 23:07 ` [PATCH v2 4/4] pinctrl: amd: remove debounce filter setting in irq type setting Coiby Xu
3 siblings, 1 reply; 7+ messages in thread
From: Coiby Xu @ 2020-11-04 23:07 UTC (permalink / raw)
To: Linus Walleij
Cc: Andy Shevchenko, Hans de Goede, open list:PIN CONTROL SUBSYSTEM,
open list
RTC is 32.768kHz thus 512 RtcClk equals 15625 usec.
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Suggested-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/linux-gpio/2f4706a1-502f-75f0-9596-cc25b4933b6c@redhat.com/
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
---
drivers/pinctrl/pinctrl-amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index d6b2b4bd337c..4aea3e05e8c6 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -156,7 +156,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
} else if (debounce < 250000) {
- time = debounce / 15600;
+ time = debounce / 15625;
pin_reg |= time & DB_TMR_OUT_MASK;
pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
pin_reg |= BIT(DB_TMR_LARGE_OFF);
--
2.28.0
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/4] pinctrl: amd: use higher precision for 512 RtcClk
2020-11-04 23:07 ` [PATCH v2 2/4] pinctrl: amd: use higher precision for 512 RtcClk Coiby Xu
@ 2020-11-05 11:13 ` Andy Shevchenko
2020-11-05 23:32 ` Coiby Xu
0 siblings, 1 reply; 7+ messages in thread
From: Andy Shevchenko @ 2020-11-05 11:13 UTC (permalink / raw)
To: Coiby Xu
Cc: Linus Walleij, Hans de Goede, open list:PIN CONTROL SUBSYSTEM, open list
On Thu, Nov 5, 2020 at 1:07 AM Coiby Xu <coiby.xu@gmail.com> wrote:
>
> RTC is 32.768kHz thus 512 RtcClk equals 15625 usec.
I could add that the documentation likely has dropped precision and
that's why the driver mistakenly took the slightly deviated value.
Anyway.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Suggested-by: Hans de Goede <hdegoede@redhat.com>
> Link: https://lore.kernel.org/linux-gpio/2f4706a1-502f-75f0-9596-cc25b4933b6c@redhat.com/
> Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
> ---
> drivers/pinctrl/pinctrl-amd.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
> index d6b2b4bd337c..4aea3e05e8c6 100644
> --- a/drivers/pinctrl/pinctrl-amd.c
> +++ b/drivers/pinctrl/pinctrl-amd.c
> @@ -156,7 +156,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
> pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
> pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
> } else if (debounce < 250000) {
> - time = debounce / 15600;
> + time = debounce / 15625;
> pin_reg |= time & DB_TMR_OUT_MASK;
> pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
> pin_reg |= BIT(DB_TMR_LARGE_OFF);
> --
> 2.28.0
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/4] pinctrl: amd: use higher precision for 512 RtcClk
2020-11-05 11:13 ` Andy Shevchenko
@ 2020-11-05 23:32 ` Coiby Xu
0 siblings, 0 replies; 7+ messages in thread
From: Coiby Xu @ 2020-11-05 23:32 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Linus Walleij, Hans de Goede, open list:PIN CONTROL SUBSYSTEM, open list
On Thu, Nov 05, 2020 at 01:13:07PM +0200, Andy Shevchenko wrote:
>On Thu, Nov 5, 2020 at 1:07 AM Coiby Xu <coiby.xu@gmail.com> wrote:
>>
>> RTC is 32.768kHz thus 512 RtcClk equals 15625 usec.
>
>I could add that the documentation likely has dropped precision and
>that's why the driver mistakenly took the slightly deviated value.
>
Thank you for the suggestion and other fixes in patch 4/4. Applied in v3.
>Anyway.
>Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
>
>> Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
>> Suggested-by: Hans de Goede <hdegoede@redhat.com>
>> Link: https://lore.kernel.org/linux-gpio/2f4706a1-502f-75f0-9596-cc25b4933b6c@redhat.com/
>> Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
>> ---
>> drivers/pinctrl/pinctrl-amd.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
>> index d6b2b4bd337c..4aea3e05e8c6 100644
>> --- a/drivers/pinctrl/pinctrl-amd.c
>> +++ b/drivers/pinctrl/pinctrl-amd.c
>> @@ -156,7 +156,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
>> pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
>> pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
>> } else if (debounce < 250000) {
>> - time = debounce / 15600;
>> + time = debounce / 15625;
>> pin_reg |= time & DB_TMR_OUT_MASK;
>> pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
>> pin_reg |= BIT(DB_TMR_LARGE_OFF);
>> --
>> 2.28.0
>>
>
>
>--
>With Best Regards,
>Andy Shevchenko
--
Best regards,
Coiby
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v2 3/4] pinctrl: amd: print debounce filter info in debugfs
[not found] <20201104230703.21466-1-coiby.xu@gmail.com>
2020-11-04 23:07 ` [PATCH v2 1/4] pinctrl: amd: fix incorrect way to disable debounce filter Coiby Xu
2020-11-04 23:07 ` [PATCH v2 2/4] pinctrl: amd: use higher precision for 512 RtcClk Coiby Xu
@ 2020-11-04 23:07 ` Coiby Xu
2020-11-04 23:07 ` [PATCH v2 4/4] pinctrl: amd: remove debounce filter setting in irq type setting Coiby Xu
3 siblings, 0 replies; 7+ messages in thread
From: Coiby Xu @ 2020-11-04 23:07 UTC (permalink / raw)
To: Linus Walleij; +Cc: Andy Shevchenko, open list:PIN CONTROL SUBSYSTEM, open list
Print the status of debounce filter as follows,
$ cat /sys/kernel/debug/gpio
pin129 interrupt is disabled| interrupt is masked| disable wakeup in S0i3 state| disable wakeup in S3 state|
disable wakeup in S4/S5 state| input is high| pull-up is disabled| Pull-down is disabled| output is disabled| debouncing filter disabled| 0x50000
^^^^^^^^^^^^^^^^^^^^^^^^^^
pin130 interrupt is disabled| interrupt is masked| disable wakeup in S0i3 state| disable wakeup in S3 state|
disable wakeup in S4/S5 state| input is high| pull-up is disabled| Pull-down is disabled| output is disabled| debouncing filter (high) enabled| debouncing timeout is 124800 (us)| 0x503c8
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
---
drivers/pinctrl/pinctrl-amd.c | 43 +++++++++++++++++++++++++++++++++--
1 file changed, 41 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 4aea3e05e8c6..e9b761c2b77a 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -197,10 +197,16 @@ static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
{
u32 pin_reg;
+ u32 db_cntrl;
unsigned long flags;
unsigned int bank, i, pin_num;
struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ bool tmr_out_unit;
+ unsigned int time;
+ unsigned int unit;
+ bool tmr_large;
+
char *level_trig;
char *active_level;
char *interrupt_enable;
@@ -214,6 +220,8 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
char *pull_down_enable;
char *output_value;
char *output_enable;
+ char debounce_value[40];
+ char *debounce_enable;
for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
seq_printf(s, "GPIO bank%d\t", bank);
@@ -327,13 +335,44 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
pin_sts = "input is low|";
}
+ db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg;
+ if (db_cntrl) {
+ tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF);
+ tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF);
+ time = pin_reg & DB_TMR_OUT_MASK;
+ if (tmr_large) {
+ if (tmr_out_unit)
+ unit = 62500;
+ else
+ unit = 15625;
+ } else {
+ if (tmr_out_unit)
+ unit = 244;
+ else
+ unit = 61;
+ }
+ if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl)
+ debounce_enable = "debouncing filter (high and low) enabled|";
+ else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl)
+ debounce_enable = "debouncing filter (low) enabled|";
+ else
+ debounce_enable = "debouncing filter (high) enabled|";
+
+ snprintf(debounce_value, sizeof(debounce_value),
+ "debouncing timeout is %u (us)|", time * unit);
+ } else {
+ debounce_enable = "debouncing filter disabled|";
+ snprintf(debounce_value, sizeof(debounce_value), " ");
+ }
+
seq_printf(s, "%s %s %s %s %s %s\n"
- " %s %s %s %s %s %s %s 0x%x\n",
+ " %s %s %s %s %s %s %s %s %s 0x%x\n",
level_trig, active_level, interrupt_enable,
interrupt_mask, wake_cntrl0, wake_cntrl1,
wake_cntrl2, pin_sts, pull_up_sel,
pull_up_enable, pull_down_enable,
- output_value, output_enable, pin_reg);
+ output_value, output_enable,
+ debounce_enable, debounce_value, pin_reg);
}
}
}
--
2.28.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v2 4/4] pinctrl: amd: remove debounce filter setting in irq type setting
[not found] <20201104230703.21466-1-coiby.xu@gmail.com>
` (2 preceding siblings ...)
2020-11-04 23:07 ` [PATCH v2 3/4] pinctrl: amd: print debounce filter info in debugfs Coiby Xu
@ 2020-11-04 23:07 ` Coiby Xu
2020-11-05 11:13 ` Andy Shevchenko
3 siblings, 1 reply; 7+ messages in thread
From: Coiby Xu @ 2020-11-04 23:07 UTC (permalink / raw)
To: Linus Walleij
Cc: Andy Shevchenko, Hans de Goede, Benjamin Tissoires,
open list:PIN CONTROL SUBSYSTEM, open list
Debounce filter setting should be independent from irq type setting
because according to the ACPI specs, there are separate arguments for
specifying debounce timeout and irq type in GpioIo and GpioInt.
This will fix broken touchpads for Lenovo Legion-5 AMD gaming laptops
including 15ARH05 (R7000) and R7000P whose BIOS set the debounce timeout
to 124.8ms which led to the kernel receiving only ~7 HID reports per
second.
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com>
BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1887190
Link: https://lore.kernel.org/linux-gpio/CAHp75VcwiGREBUJ0A06EEw-SyabqYsp%2Bdqs2DpSrhaY-2GVdAA%40mail.gmail.com/
Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
---
drivers/pinctrl/pinctrl-amd.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index e9b761c2b77a..2d4acf21117c 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -468,7 +468,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
- pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -476,7 +475,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
- pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -484,7 +482,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg &= ~BIT(LEVEL_TRIG_OFF);
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
- pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_edge_irq);
break;
@@ -492,8 +489,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
- pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
- pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
@@ -501,8 +496,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
- pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
- pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
irq_set_handler_locked(d, handle_level_irq);
break;
--
2.28.0
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 4/4] pinctrl: amd: remove debounce filter setting in irq type setting
2020-11-04 23:07 ` [PATCH v2 4/4] pinctrl: amd: remove debounce filter setting in irq type setting Coiby Xu
@ 2020-11-05 11:13 ` Andy Shevchenko
0 siblings, 0 replies; 7+ messages in thread
From: Andy Shevchenko @ 2020-11-05 11:13 UTC (permalink / raw)
To: Coiby Xu
Cc: Linus Walleij, Hans de Goede, Benjamin Tissoires,
open list:PIN CONTROL SUBSYSTEM, open list
On Thu, Nov 5, 2020 at 1:07 AM Coiby Xu <coiby.xu@gmail.com> wrote:
>
> Debounce filter setting should be independent from irq type setting
> because according to the ACPI specs, there are separate arguments for
> specifying debounce timeout and irq type in GpioIo and GpioInt.
irq -> IRQ
GpioIo()
GpioInt()
> This will fix broken touchpads for Lenovo Legion-5 AMD gaming laptops
> including 15ARH05 (R7000) and R7000P whose BIOS set the debounce timeout
> to 124.8ms which led to the kernel receiving only ~7 HID reports per
> second.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Benjamin Tissoires <benjamin.tissoires@redhat.com>
> BugLink: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1887190
> Link: https://lore.kernel.org/linux-gpio/CAHp75VcwiGREBUJ0A06EEw-SyabqYsp%2Bdqs2DpSrhaY-2GVdAA%40mail.gmail.com/
> Signed-off-by: Coiby Xu <coiby.xu@gmail.com>
> ---
> drivers/pinctrl/pinctrl-amd.c | 7 -------
> 1 file changed, 7 deletions(-)
>
> diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
> index e9b761c2b77a..2d4acf21117c 100644
> --- a/drivers/pinctrl/pinctrl-amd.c
> +++ b/drivers/pinctrl/pinctrl-amd.c
> @@ -468,7 +468,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> pin_reg &= ~BIT(LEVEL_TRIG_OFF);
> pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
> pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
> - pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
> irq_set_handler_locked(d, handle_edge_irq);
> break;
>
> @@ -476,7 +475,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> pin_reg &= ~BIT(LEVEL_TRIG_OFF);
> pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
> pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
> - pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
> irq_set_handler_locked(d, handle_edge_irq);
> break;
>
> @@ -484,7 +482,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> pin_reg &= ~BIT(LEVEL_TRIG_OFF);
> pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
> pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
> - pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
> irq_set_handler_locked(d, handle_edge_irq);
> break;
>
> @@ -492,8 +489,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
> pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
> pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
> - pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
> - pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
> irq_set_handler_locked(d, handle_level_irq);
> break;
>
> @@ -501,8 +496,6 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
> pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
> pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
> pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
> - pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
> - pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
> irq_set_handler_locked(d, handle_level_irq);
> break;
>
> --
> 2.28.0
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 7+ messages in thread