From: Sudeep Holla <sudeep.holla@arm.com>
To: Jim Quinlan <james.quinlan@broadcom.com>
Cc: "maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE"
<bcm-kernel-feedback-list@broadcom.com>,
Cristian Marussi <cristian.marussi@arm.com>,
Sudeep Holla <sudeep.holla@arm.com>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 2/2] firmware: arm_scmi: Augment SMC/HVC to allow optional interrupt
Date: Fri, 20 Nov 2020 11:14:27 +0000 [thread overview]
Message-ID: <20201120111427.erqfowx4rosuktao@bogus> (raw)
In-Reply-To: <CA+-6iNw2+uGX3W3boiNokbVwaK2MseJORPq8mDpc+SihoLSOQw@mail.gmail.com>
On Thu, Nov 19, 2020 at 01:34:18PM -0500, Jim Quinlan wrote:
> On Fri, Nov 13, 2020 at 10:12 AM Jim Quinlan <james.quinlan@broadcom.com> wrote:
> >
> > On Fri, Nov 13, 2020 at 9:36 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > >
> > > On Fri, Nov 13, 2020 at 09:26:43AM -0500, Jim Quinlan wrote:
> > > > Hi, these are fast calls. Regards, Jim
> > > >
> > > >
> > > > On Fri, Nov 13, 2020 at 4:47 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > > > >
> > > > > On Thu, Nov 12, 2020 at 12:56:27PM -0500, Jim Quinlan wrote:
> > > > > > The SMC/HVC SCMI transport is modified to allow the completion of an SCMI
> > > > > > message to be indicated by an interrupt rather than the return of the smc
> > > > > > call. This accommodates the existing behavior of the BrcmSTB SCMI
> > > > > > "platform" whose SW is already out in the field and cannot be changed.
> > > > > >
> > > > >
> > > > > Sorry for missing to check with you earlier. Are these not fast smc calls ?
> > > > > Can we check the SMC Function IDs for the same and expect IRQ to be present
> > > > > if they are not fast calls ?
> > > > Hi, if I understand you correctly you want to do something like this:
> > > >
> > > > if (! ARM_SMCCC_IS_FAST_CALL(func_id)) {
> > > > /* look for irq and request it */
> > > > }
> > > >
> > >
> > > Yes.
> > >
> > > > But we do use fast calls.
> > >
> > > What was the rationale for retaining fast SMC calls but use IRQ for Tx
> > > completion ?
> > >
> > > Is it because you offload it to some other microprocessor and don't
> > > continue execution on secure side in whcih case you can afford fast call ?
> Hi Sudeep,
>
Thanks for the details. Unfortunately more questions:
> Here is my understanding: Some SMC calls may take a few longer to
> complete than others. The longer ones tie up the CPU core that is
> handling the SMC call, and so nothing can be scheduled on that
> specific core.
So far good.
> Unfortunately, we have a real-time OS that runs
> sporadically on one specific core and if that happens to be the same
> core that is handling the SMC, the RTOS will miss its deadline. So we
> need to have the SMC return immediately and use an SGI for task
> completion.
>
So it sounds more like it can't be fast call then.
Does that me, it will always return early and send SGI when the request
is complete ?
1. If yes, what happens if there are multiple requests in parallel and
second one completes before the first. Can we handle that with this
patch set. Of will the second request fails until the first one is
complete ? It extends to number of cpus in the system worst case.
2. If no, will this not cause issues if we unconditional wait for interrupt
every single time ?
--
Regards,
Sudeep
next prev parent reply other threads:[~2020-11-20 11:14 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-12 17:56 [PATCH v2 0/2] " Jim Quinlan
2020-11-12 17:56 ` [PATCH v2 1/2] dt-bindings: arm: Add optional interrupt to smc/hvc SCMI transport Jim Quinlan
2020-11-20 17:20 ` Jim Quinlan
2020-12-07 19:01 ` Rob Herring
2020-12-07 19:49 ` Jim Quinlan
2020-11-12 17:56 ` [PATCH v2 2/2] firmware: arm_scmi: Augment SMC/HVC to allow optional interrupt Jim Quinlan
2020-11-13 9:47 ` Sudeep Holla
2020-11-13 14:26 ` Jim Quinlan
2020-11-13 14:36 ` Sudeep Holla
2020-11-13 15:12 ` Jim Quinlan
2020-11-19 18:34 ` Jim Quinlan
2020-11-20 11:14 ` Sudeep Holla [this message]
2020-11-20 13:27 ` Jim Quinlan
2020-11-20 14:09 ` Sudeep Holla
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