From: Kishon Vijay Abraham I <kishon@ti.com>
To: Tero Kristo <t-kristo@ti.com>, Nishanth Menon <nm@ti.com>,
Rob Herring <robh+dt@kernel.org>,
Kishon Vijay Abraham I <kishon@ti.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 4/6] arm64: dts: ti: k3-j7200-main: Add PCIe device tree node
Date: Thu, 10 Dec 2020 18:37:45 +0530 [thread overview]
Message-ID: <20201210130747.25436-5-kishon@ti.com> (raw)
In-Reply-To: <20201210130747.25436-1-kishon@ti.com>
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 48 +++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index ae5abf59a7d4..819aa1fc306b 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -592,6 +592,54 @@
};
};
+ pcie1_rc: pcie@2910000 {
+ compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x00001000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ device_type = "pci";
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xf>;
+ cdns,no-bar-match-nbits = <64>;
+ vendor-id = /bits/ 16 <0x104c>;
+ device-id = /bits/ 16 <0xb00f>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ dma-coherent;
+ ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
+ <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+ };
+
+ pcie1_ep: pcie-ep@2910000 {
+ compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+ reg = <0x00 0x02910000 0x00 0x1000>,
+ <0x00 0x02917000 0x00 0x400>,
+ <0x00 0x0d800000 0x00 0x00800000>,
+ <0x00 0x18000000 0x00 0x08000000>;
+ reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+ interrupt-names = "link_state";
+ interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+ ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
+ max-link-speed = <3>;
+ num-lanes = <4>;
+ power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 240 6>;
+ clock-names = "fck";
+ max-functions = /bits/ 8 <6>;
+ dma-coherent;
+ };
+
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;
--
2.17.1
next prev parent reply other threads:[~2020-12-10 13:12 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-10 13:07 [PATCH v2 0/6] PCI: J7200/J721E PCIe bindings Kishon Vijay Abraham I
2020-12-10 13:07 ` [PATCH v2 1/6] arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions Kishon Vijay Abraham I
2020-12-10 13:07 ` [PATCH v2 2/6] arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for pcieX_ctrl Kishon Vijay Abraham I
2020-12-10 13:07 ` [PATCH v2 3/6] arm64: dts: ti: k3-j7200-main: Add DT for WIZ and SERDES Kishon Vijay Abraham I
2020-12-10 13:07 ` Kishon Vijay Abraham I [this message]
2020-12-10 13:07 ` [PATCH v2 5/6] arm64: dts: ti: k3-j7200-common-proc-board: Enable SERDES0 Kishon Vijay Abraham I
2020-12-10 13:07 ` [PATCH v2 6/6] arm64: dts: ti: k3-j7200-common-proc-board: Enable PCIe Kishon Vijay Abraham I
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