From: Filippo Sironi <sironi@amazon.de>
To: <serebrin@amazon.com>, <dwmw@amazon.co.uk>, <kbusch@kernel.org>,
<axboe@fb.com>, <hch@lst.de>, <sagi@grimberg.me>,
<linux-nvme@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Cc: Filippo Sironi <sironi@amazon.de>
Subject: [PATCH] nvme: Add 48-bit DMA address quirk
Date: Wed, 3 Feb 2021 10:43:38 +0100 [thread overview]
Message-ID: <20210203094338.19473-1-sironi@amazon.de> (raw)
Certain NVMe controllers don't support 64-bit DMA addresses. Instead,
they are limited to 48-bit DMA addresses. Let's add a quirk to use them
properly.
Signed-off-by: Filippo Sironi <sironi@amazon.de>
---
drivers/nvme/host/nvme.h | 5 +++++
drivers/nvme/host/pci.c | 12 +++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
index 88a6b97247f5..dae747b4ac35 100644
--- a/drivers/nvme/host/nvme.h
+++ b/drivers/nvme/host/nvme.h
@@ -144,6 +144,11 @@ enum nvme_quirks {
* NVMe 1.3 compliance.
*/
NVME_QUIRK_NO_NS_DESC_LIST = (1 << 15),
+
+ /*
+ * The controller supports up to 48-bit DMA address.
+ */
+ NVME_QUIRK_DMA_ADDRESS_BITS_48 = (1 << 16),
};
/*
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
index 81e6389b2042..5716ae16c7a7 100644
--- a/drivers/nvme/host/pci.c
+++ b/drivers/nvme/host/pci.c
@@ -2362,13 +2362,16 @@ static int nvme_pci_enable(struct nvme_dev *dev)
{
int result = -ENOMEM;
struct pci_dev *pdev = to_pci_dev(dev->dev);
+ int dma_address_bits = 64;
if (pci_enable_device_mem(pdev))
return result;
pci_set_master(pdev);
- if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
+ if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
+ dma_address_bits = 48;
+ if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
goto disable;
if (readl(dev->bar + NVME_REG_CSTS) == -1) {
@@ -3259,6 +3262,13 @@ static const struct pci_device_id nvme_id_table[] = {
.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
{ PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
+ { .vendor = PCI_VENDOR_ID_AMAZON,
+ .device = PCI_ANY_ID,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+ .class = PCI_CLASS_STORAGE_EXPRESS,
+ .class_mask = 0xffffff,
+ .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48 },
{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
.driver_data = NVME_QUIRK_SINGLE_VECTOR },
{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
--
2.17.1
Amazon Development Center Germany GmbH
Krausenstr. 38
10117 Berlin
Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss
Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B
Sitz: Berlin
Ust-ID: DE 289 237 879
next reply other threads:[~2021-02-03 9:45 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-03 9:43 Filippo Sironi [this message]
2021-02-03 9:51 ` Christoph Hellwig
2021-02-03 11:12 ` Filippo Sironi
2021-02-03 11:15 ` Christoph Hellwig
2021-02-03 11:22 ` Filippo Sironi
2021-02-03 11:26 ` Christoph Hellwig
2021-02-03 16:57 ` Keith Busch
2021-02-10 0:39 ` [PATCH v2] nvme: Add 48-bit DMA address quirk for Amazon NVMe controllers Filippo Sironi
2021-02-10 7:37 ` Christoph Hellwig
2021-02-10 9:13 ` Filippo Sironi
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