From: Yazen Ghannam <yazen.ghannam@amd.com>
To: linux-edac@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, bp@alien8.de, mchehab@kernel.org,
tony.luck@intel.com, Smita.KoralahalliChannabasappa@amd.com,
Yazen Ghannam <yazen.ghannam@amd.com>
Subject: [PATCH v2 09/31] EDAC/amd64: Define function to find interleaving mode
Date: Wed, 23 Jun 2021 19:19:40 +0000 [thread overview]
Message-ID: <20210623192002.3671647-10-yazen.ghannam@amd.com> (raw)
In-Reply-To: <20210623192002.3671647-1-yazen.ghannam@amd.com>
Define a helper function to find the interleaving mode. Define a
DF2-specific function now. Future DF versions will have their own
functions.
Use an enumeration for the interleaving modes to give a human-readable
value. Save the interleaving mode in the context struct, since this will
be used in multiple functions.
Multiple interleaving modes support hashing, so save a boolean in the
context struct to check if hashing is enabled.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20210507190140.18854-6-Yazen.Ghannam@amd.com
v1->v2:
* Moved from arch/x86 to EDAC.
* Add new function to data_fabric_ops.
drivers/edac/amd64_edac.c | 35 ++++++++++++++++++++++++++++++++---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 867ab32caab2..93a4ce9eb735 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -1079,8 +1079,16 @@ static struct df_reg df_regs[] = {
[SYS_FAB_ID_MASK] = {1, 0x208},
};
+/* These are mapped 1:1 to the hardware values. Special cases are set at > 0x20. */
+enum intlv_modes {
+ NONE = 0x00,
+ NOHASH_2CH = 0x01,
+ DF2_HASH_2CH = 0x21,
+};
+
/* Use "reg_" prefix for raw register values. */
struct addr_ctx {
+ enum intlv_modes intlv_mode;
u64 ret_addr;
u32 reg_dram_offset;
u32 reg_base_addr;
@@ -1088,10 +1096,12 @@ struct addr_ctx {
u16 nid;
u8 inst_id;
u8 map_num;
+ bool hash_enabled;
};
struct data_fabric_ops {
u64 (*get_hi_addr_offset)(struct addr_ctx *ctx);
+ int (*get_intlv_mode)(struct addr_ctx *ctx);
};
static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx)
@@ -1099,8 +1109,26 @@ static u64 get_hi_addr_offset_df2(struct addr_ctx *ctx)
return (ctx->reg_dram_offset & GENMASK_ULL(31, 20)) << 8;
}
+static int get_intlv_mode_df2(struct addr_ctx *ctx)
+{
+ ctx->intlv_mode = (ctx->reg_base_addr >> 4) & 0xF;
+
+ if (ctx->intlv_mode == 8) {
+ ctx->intlv_mode = DF2_HASH_2CH;
+ ctx->hash_enabled = true;
+ }
+
+ if (ctx->intlv_mode != NONE &&
+ ctx->intlv_mode != NOHASH_2CH &&
+ ctx->intlv_mode != DF2_HASH_2CH)
+ return -EINVAL;
+
+ return 0;
+}
+
struct data_fabric_ops df2_ops = {
.get_hi_addr_offset = &get_hi_addr_offset_df2,
+ .get_intlv_mode = &get_intlv_mode_df2,
};
struct data_fabric_ops *df_ops;
@@ -1176,7 +1204,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
u8 num_intlv_bits, hashed_bit;
u8 lgcy_mmio_hole_en;
u8 cs_mask, cs_id = 0;
- bool hash_enabled = false;
struct addr_ctx ctx;
@@ -1197,6 +1224,9 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
if (get_dram_addr_map(&ctx))
goto out_err;
+ if (df_ops->get_intlv_mode(&ctx))
+ goto out_err;
+
lgcy_mmio_hole_en = ctx.reg_base_addr & BIT(1);
intlv_num_chan = (ctx.reg_base_addr >> 4) & 0xF;
intlv_addr_sel = (ctx.reg_base_addr >> 8) & 0x7;
@@ -1224,7 +1254,6 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
case 7: intlv_num_chan = 4; break;
case 8: intlv_num_chan = 1;
- hash_enabled = true;
break;
default:
pr_err("%s: Invalid number of interleaved channels %d.\n",
@@ -1325,7 +1354,7 @@ static int umc_normaddr_to_sysaddr(u64 norm_addr, u16 nid, u8 umc, u64 *sys_addr
ctx.ret_addr += (BIT_ULL(32) - dram_hole_base);
}
- if (hash_enabled) {
+ if (ctx.hash_enabled) {
/* Save some parentheses and grab ls-bit at the end. */
hashed_bit = (ctx.ret_addr >> 12) ^
(ctx.ret_addr >> 18) ^
--
2.25.1
next prev parent reply other threads:[~2021-06-23 19:21 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-23 19:19 [PATCH v2 00/31] AMD MCA Address Translation Updates Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 01/31] x86/MCE/AMD, EDAC/amd64: Move address translation to AMD64 EDAC Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 02/31] x86/amd_nb, EDAC/amd64: Move DF Indirect Read " Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 03/31] EDAC/amd64: Don't use naked values for DF registers Yazen Ghannam
2021-06-25 15:21 ` Borislav Petkov
2021-07-08 19:35 ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 04/31] EDAC/amd64: Allow for DF Indirect Broadcast reads Yazen Ghannam
2021-06-30 16:22 ` Borislav Petkov
2021-07-08 19:44 ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 05/31] EDAC/amd64: Add context struct Yazen Ghannam
2021-06-30 17:17 ` Borislav Petkov
2021-07-08 19:53 ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 06/31] EDAC/amd64: Define Data Fabric operations Yazen Ghannam
2021-06-30 17:19 ` Borislav Petkov
2021-07-08 19:55 ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 07/31] EDAC/amd64: Define functions for DramOffset Yazen Ghannam
2021-06-30 17:27 ` Borislav Petkov
2021-07-08 20:08 ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 08/31] EDAC/amd64: Define function to read DRAM address map registers Yazen Ghannam
2021-06-30 17:29 ` Borislav Petkov
2021-06-23 19:19 ` Yazen Ghannam [this message]
2021-06-30 17:33 ` [PATCH v2 09/31] EDAC/amd64: Define function to find interleaving mode Borislav Petkov
2021-07-08 20:09 ` Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 10/31] EDAC/amd64: Define function to denormalize address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 11/31] EDAC/amd64: Define function to add DRAM base and hole Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 12/31] EDAC/amd64: Define function to dehash address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 13/31] EDAC/amd64: Define function to check DRAM limit address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 14/31] EDAC/amd64: Remove goto statements Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 15/31] EDAC/amd64: Simplify function parameters Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 16/31] EDAC/amd64: Define function to get Interleave Address Bit Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 17/31] EDAC/amd64: Skip denormalization if no interleaving Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 18/31] EDAC/amd64: Define function to get number of interleaved channels Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 19/31] EDAC/amd64: Define function to get number of interleaved dies Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 20/31] EDAC/amd64: Define function to get number of interleaved sockets Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 21/31] EDAC/amd64: Remove unnecessary assert Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 22/31] EDAC/amd64: Define function to make space for CS ID Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 23/31] EDAC/amd64: Define function to calculate " Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 24/31] EDAC/amd64: Define function to insert CS ID into address Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 25/31] EDAC/amd64: Define function to get CS Fabric ID Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 26/31] EDAC/amd64: Define function to find shift and mask values Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 27/31] EDAC/amd64: Update CS ID calculation to match reference code Yazen Ghannam
2021-06-23 19:19 ` [PATCH v2 28/31] EDAC/amd64: Match hash function to " Yazen Ghannam
2021-06-23 19:20 ` [PATCH v2 29/31] EDAC/amd64: Define helper function to get interleave address select bit Yazen Ghannam
2021-06-23 19:20 ` [PATCH v2 30/31] EDAC/amd64: Add support for address translation on DF3 systems Yazen Ghannam
2021-06-23 19:20 ` [PATCH v2 31/31] EDAC/amd64: Add glossary of acronyms for address translation Yazen Ghannam
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